Display after a blocking statement

Parch,

You may be surprised that the monitor statement doesn't trigger
immediately after the assignment:

#2 a = 1;

Instead it seems to fall through and execute the following display
statements and maybe "a" is somehow not assigned. Rest assured that it
is. The reason the monitor statement doesn't print the message is that
monitor events don't get executed until all active and inactive events
get executed. After the blocking assignment takes place, the display
statements are active so the monitor message won't be printed until
the very end of the timestep 2. Take a look at the section on
"Scheduling Semantics" in the LRM or a book like Thomas & Moorsby for
details on how events are scheduled.

David Walker

Parch wrote:
Hello,

Can anyone justify why display statement is getting executed after the
blocking assignment in the below mentioned program?

module test;

reg a;
reg b;

initial begin
$monitor("Time: %d, a = %b b = %b",$time,a,b);
a = 0;
b = 1;
$display("Before the block St");
#2 a = 1; //bds
$display("1. After the block St");
$display("2. After the block St");
$display("3. After the block St");
$display("4. After the block St");
$display("Time is %d",$time);
a = #2 0; //bsd
$display("Time is %d",$time);
a <= #3 b; //nbsd
$display("Time is %d",$time);
#1 b = 0; //bds
$display("Time is %d",$time);
#5 $finish;
end

endmodule


Output
Running...
Before the block St
Time: 0, a = 0 b = 1
1. After the block St
2. After the block St
3. After the block St
4. After the block St
Time is 2
Time: 2, a = 1 b = 1
Time is 4
Time is 4
Time: 4, a = 0 b = 1
Time is 5
Time: 5, a = 0 b = 0
Time: 7, a = 1 b = 0
Exiting TestBencher Pro at simulation time 10000
0 Errors, 0 Warnings
Compile time = 0.00000, Load time = 0.01600, Execution time = 0.01600

Normal exit
Click to expand...
 
P

Parch

Guest
Hello,

Can anyone justify why display statement is getting executed after the
blocking assignment in the below mentioned program?

module test;

reg a;
reg b;

initial begin
$monitor("Time: %d, a = %b b = %b",$time,a,b);
a = 0;
b = 1;
$display("Before the block St");
#2 a = 1; //bds
$display("1. After the block St");
$display("2. After the block St");
$display("3. After the block St");
$display("4. After the block St");
$display("Time is %d",$time);
a = #2 0; //bsd
$display("Time is %d",$time);
a <= #3 b; //nbsd
$display("Time is %d",$time);
#1 b = 0; //bds
$display("Time is %d",$time);
#5 $finish;
end

endmodule


<Output>
Running...
Before the block St
Time: 0, a = 0 b = 1
1. After the block St
2. After the block St
3. After the block St
4. After the block St
Time is 2
Time: 2, a = 1 b = 1
Time is 4
Time is 4
Time: 4, a = 0 b = 1
Time is 5
Time: 5, a = 0 b = 0
Time: 7, a = 1 b = 0
Exiting TestBencher Pro at simulation time 10000
0 Errors, 0 Warnings
Compile time = 0.00000, Load time = 0.01600, Execution time = 0.01600

Normal exit
 
On Sun, 04 Nov 2007 03:27:15 -0800, Parch <partha.maji@gmail.com>
wrote:

Hello,

Can anyone justify why display statement is getting executed after the
blocking assignment in the below mentioned program?
Click to expand...
After *which* blocking assignment?

What do you think is unexpected about the result?
It appears to be what I would expect.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
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