Discussion "Async Reset"

[ALuPin]

Hi @ all,

I have read the discussion "Async Reset".

There it has been mentioned that it is one possibility to
synchronize an asynchronous reset so that all flip flops in
the FPGA are resetted within the same clock period.

Using this synchronized reset
can I still write the process like that:


process(Sync_reset, Clk)
begin
if Sync_reset='1' then
...
elsif rising_edge(Clk) then
...
end if;

end process;

or does it make more sense to write it like that:

process(Sync_reset, CLk)
begin
if rising_edge(Clk) then
if Sync_reset='1' then
...
else
...
end if;
end if;
end process;

I would be very thankful for your opinion.

Rgds
André

 

[Raghavendra]

ALuPin@web.de (ALuPin) wrote in message news:<b8a9a7b0.0410250318.61e6ae47@posting.google.com>...

Hi @ all,

I have read the discussion "Async Reset".

There it has been mentioned that it is one possibility to
synchronize an asynchronous reset so that all flip flops in
the FPGA are resetted within the same clock period.

Using this synchronized reset
can I still write the process like that:


process(Sync_reset, Clk)
begin
if Sync_reset='1' then
...
elsif rising_edge(Clk) then
...
end if;

end process;

or does it make more sense to write it like that:

process(Sync_reset, CLk)
begin
if rising_edge(Clk) then
if Sync_reset='1' then
...
else
...
end if;
end if;
end process;

I would be very thankful for your opinion.

Rgds
André

HI,
To avoid problems with asynchronous reset you can have asynchronous
reset assert and synchronous dessert using synchronizers.
Raghavendra.Sortur