[discuss] verilog code to synthesis

Y

Yang Luo

Guest
Now I'm writing some rtl code, there are some written styles puzzle me. Can you give me some advise?
I'm translating an algorithm into atl and making an ASIC. I'm very worry about whether the code I written can be sythesised using EDA tools.

There are some code block like this:
2.parameter BIT_WIDTH = 8;
parameter BUFF_LENGTH = 16;
input [BIT_WIDTH-1:0] i_data;
reg [BIT_WIDTH-1:0] s_data_buff [BUFF_LENGTH-1:0];
integer i;
2.1
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
for(i=0; i< BUFF_LENGTH; i=i+1)s_data_buff <= #1 {BIT_WIDTH{1'd0}};
end
else begin
s_data_buff[0] <= #1 i_data;
for(i=0; i< BUFF_LENGTH-1;i=i+1)s_data_buff[i+1] <= #1 s_data_buff;
end
2.2
wire [3:0] w_buff_length;//0--15
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
for(i=0; i< w_buff_length; i=i+1)s_data_buff <= #1 {BIT_WIDTH{1'd0}};
end
else begin
s_data_buff[0] <= #1 i_data;
for(i=0; i< w_buff_length-1;i=i+1)s_data_buff[i+1] <= #1 s_data_buff;
end

Are the two styles both good? I know that DC can synthesis the first style, because the array index is a const number. Can EDA tools synthesis the second style(I used a wire variable as index)?

3.Can the 2d array be synthesised using EDA tools in verilog? like this:
reg [BIT_WIDTH-1:0] s_data_buff2d [BUFF_LENGTH-1:0]BUFF_LENGTH-1:0];
 
In article <983d44ac-903a-4f88-aba2-f5c6f82b3821@googlegroups.com>,
Yang Luo <youngluoyang@gmail.com> wrote:
Now I'm writing some rtl code, there are some written styles puzzle me. Can you give me some advise?
I'm translating an algorithm into atl and making an ASIC. I'm very worry about whether the code I written can be sythesised using EDA tools.

There are some code block like this:
2.parameter BIT_WIDTH = 8;
parameter BUFF_LENGTH = 16;
input [BIT_WIDTH-1:0] i_data;
reg [BIT_WIDTH-1:0] s_data_buff [BUFF_LENGTH-1:0];
integer i;
2.1
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
for(i=0; i< BUFF_LENGTH; i=i+1)s_data_buff <= #1 {BIT_WIDTH{1'd0}};
end
else begin
s_data_buff[0] <= #1 i_data;
for(i=0; i< BUFF_LENGTH-1;i=i+1)s_data_buff[i+1] <= #1 s_data_buff;
end
2.2
wire [3:0] w_buff_length;//0--15
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
for(i=0; i< w_buff_length; i=i+1)s_data_buff <= #1 {BIT_WIDTH{1'd0}};
end
else begin
s_data_buff[0] <= #1 i_data;
for(i=0; i< w_buff_length-1;i=i+1)s_data_buff[i+1] <= #1 s_data_buff;
end

Are the two styles both good? I know that DC can synthesis the first style,
because the array index is a const number. Can EDA tools synthesis the second
style(I used a wire variable as index)?
Click to expand...


For loops must be (in software terms) "unrolled" at elaboration time during
synthesis. So for your second case to work, firstly, "w_buff_length" must be a constant
at elaboration time. Secondly, even if it was a constant at elaboration time, the
tool would have to support this type of "unrolling". I'm doubtful any synthesis
tools would succeed on the second point. I'd think they'd flag an error.

3.Can the 2d array be synthesised using EDA tools in verilog? like this:
reg [BIT_WIDTH-1:0] s_data_buff2d [BUFF_LENGTH-1:0]BUFF_LENGTH-1:0];
Click to expand...

All synthesis tools (that I've used) can handle 2-d arrays fine. Are you asking
about a 3-d array? (Your example seems to imply two "unpacked" dimensions.) I'm
unsure on Synthesis support (under verilog-2001) for this. It WOULD work fine
by turning on SystemVerilog support under your tool.

May I also suggest training yourself to NOT use #delays within
synthesizable code. They're entirely unneccesary, and often seen as a
crutch for new users. They're not harmful, and can make viewing waveforums
easier for new users. But are generally avoided by most users.

Regards,

Mark
 
在 2016年3月16日星期三 UTC+8上午4:25:27，Mark Curry写道：
In article <983d44ac-903a-4f88-aba2-f5c6f82b3821@googlegroups.com>,
Yang Luo <youngluoyang@gmail.com> wrote:
Now I'm writing some rtl code, there are some written styles puzzle me. Can you give me some advise?
I'm translating an algorithm into atl and making an ASIC. I'm very worry about whether the code I written can be sythesised using EDA tools.

There are some code block like this:
2.parameter BIT_WIDTH = 8;
parameter BUFF_LENGTH = 16;
input [BIT_WIDTH-1:0] i_data;
reg [BIT_WIDTH-1:0] s_data_buff [BUFF_LENGTH-1:0];
integer i;
2.1
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
for(i=0; i< BUFF_LENGTH; i=i+1)s_data_buff <= #1 {BIT_WIDTH{1'd0}};
end
else begin
s_data_buff[0] <= #1 i_data;
for(i=0; i< BUFF_LENGTH-1;i=i+1)s_data_buff[i+1] <= #1 s_data_buff;
end
2.2
wire [3:0] w_buff_length;//0--15
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
for(i=0; i< w_buff_length; i=i+1)s_data_buff <= #1 {BIT_WIDTH{1'd0}};
end
else begin
s_data_buff[0] <= #1 i_data;
for(i=0; i< w_buff_length-1;i=i+1)s_data_buff[i+1] <= #1 s_data_buff;
end

Are the two styles both good? I know that DC can synthesis the first style,
because the array index is a const number. Can EDA tools synthesis the second
style(I used a wire variable as index)?

For loops must be (in software terms) "unrolled" at elaboration time during
synthesis. So for your second case to work, firstly, "w_buff_length" must be a constant
at elaboration time. Secondly, even if it was a constant at elaboration time, the
tool would have to support this type of "unrolling". I'm doubtful any synthesis
tools would succeed on the second point. I'd think they'd flag an error.

3.Can the 2d array be synthesised using EDA tools in verilog? like this:
reg [BIT_WIDTH-1:0] s_data_buff2d [BUFF_LENGTH-1:0]BUFF_LENGTH-1:0];
Click to expand...

Yes, this 3d array can not synthesis using DC2010. I tested using such example:
integer i,j;
always@(posedge clk or negedge rst_n)
if(!rst_n)begin
for (i=0;i<BUFF_LENGTH;i=i+1)
for (j=0;j<BUFF_LENGTH;j=j+1)
s_data_buff2d [j]<=0;
end
....
when synthesis, it will give an error that index i or j over BUFF_LENGTH.
All synthesis tools (that I've used) can handle 2-d arrays fine. Are you asking
about a 3-d array? (Your example seems to imply two "unpacked" dimensions..) I'm
unsure on Synthesis support (under verilog-2001) for this. It WOULD work fine
by turning on SystemVerilog support under your tool.

May I also suggest training yourself to NOT use #delays within
synthesizable code. They're entirely unneccesary, and often seen as a
crutch for new users. They're not harmful, and can make viewing waveforums
easier for new users. But are generally avoided by most users.
#delay is not my style.

Regards,

Mark
Click to expand...
 
hello, in my opinion, I think you should try to think how your code will be synthesized to what kind of difital circuits, it is more helpful for you, sometimes the synthesizer maybe not easy to P&R, so the result is not as your thought.
 
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