disadvantages of inferring latches

[ronhk25]

Hi all,

I always hear from FPGA designers that latches are "dangerous" and that it's very important avoiding them. I wonder what are the technical risks resulting by using latches. As far as I understand, the main problem is that FPGAs don't have built in hard latches so the synthesizer has to implement it from logic blocks and then the race condition in the resulting logic is hard/impossible to be analyzed.
Is this main disadvantage latches? are there any other issues regarding latches which shall be considered?

Thanks,

Ron

 

[KJ]

You've got it almost correct. The only mistake is that it's not that they are 'hard/impossible to be analyzed' though, it's because the race conditions will cause the latch to fail if constructed out of logic blocks rather than a hard latch. A flip flop would fail in the same way if constructed out of logic blocks as well.

Kevin Jennings

 

[ronhk25]

בתאריך יום שני, 17 בנובמבר 2014 11:17:04 UTC+2, מאת ronhk25:

Hi all,

I always hear from FPGA designers that latches are "dangerous" and that it's very important avoiding them. I wonder what are the technical risks resulting by using latches. As far as I understand, the main problem is that FPGAs don't have built in hard latches so the synthesizer has to implement it from logic blocks and then the race condition in the resulting logic is hard/impossible to be analyzed.
Is this main disadvantage latches? are there any other issues regarding latches which shall be considered?

Thanks,

Ron

RIK and HTH thanks for your reply,

RIK, regarding your question- in some cases while using combinatorical logic based state machines, i would like that some signals will keep their current values as a default (unless some defined conditions are met). I think that this will result with latch since we get an asynchronous process (asynchronous decoders for the next state and for the output registers) with a signal that its default value is its current value (i'm not that experinced with asynchronous design so please correct me if i'm wrong...).
I agree that latches are not sound that usefull but sometimes i find myself choosing not to use asynchronous processes in order to avoid from inferred latches.

 

[KJ]

> RIK, regarding your question- in some cases while using combinatorical logic based state machines, i would like that some signals will keep their current values as a default (unless some defined conditions are met).

This will result in a design that fails. If you're lucky it just never works, if you're not lucky you find that it doesn't work as you're manufacturing is trying to build 1000 boards and find they are 'flaky'. Take what you think to be a 'working' design' and spray some cold spray on the part and watch it fail.

If you're doing FPGA designs and you're using a part that does not have hard latches, then you would be best off to abandon any use of combinatorial state machines before you get burned.

Kevin Jennings

 

[ronhk25]

בתאריך יום שני, 17 בנובמבר 2014 11:17:04 UTC+2, מאת ronhk25:

Hi all,

I always hear from FPGA designers that latches are "dangerous" and that it's very important avoiding them. I wonder what are the technical risks resulting by using latches. As far as I understand, the main problem is that FPGAs don't have built in hard latches so the synthesizer has to implement it from logic blocks and then the race condition in the resulting logic is hard/impossible to be analyzed.
Is this main disadvantage latches? are there any other issues regarding latches which shall be considered?

Thanks,

Ron

Rick and Al thanks for your reply,

RIK, regarding your question- in some cases while using combinatorial logic based state machines, I would like that some signals will keep their current values as a default (unless some defined conditions are met). I think that this will result with latch since we get an asynchronous process (asynchronous decoders for the next state and for the output registers) with a signal that its default value is its current value (I’m not that experienced with asynchronous design so please correct me if I’m wrong....).
I agree that latches are not sound that useful but sometimes I find myself choosing not to use asynchronous processes in order to avoid from inferred latches.

 

[rickman]

On 11/17/2014 4:17 AM, ronhk25 wrote:

Hi all,

I always hear from FPGA designers that latches are "dangerous" and that it's very important avoiding them. I wonder what are the technical risks resulting by using latches. As far as I understand, the main problem is that FPGAs don't have built in hard latches so the synthesizer has to implement it from logic blocks and then the race condition in the resulting logic is hard/impossible to be analyzed.
Is this main disadvantage latches? are there any other issues regarding latches which shall be considered?

It is not that latches are inherently bad. The problem is that they can
be inferred unintentionally. The only time I remember using a latch in
a design was way back when the 8085 CPU was around. I recall that they
multiplexed the address with the data or with itself (upper/lower) and
to get the best address setup time a latch was used, 74LS373 rather than
the 74LS374 register. The address would flow through ahead of the edge
of the clock that would hold it giving more address setup time.

I believe that most programmable logic will implement latches ok. I'm
not sure what race condition you are referring to. The only problem I
can see is that if you use them in the wrong place they will let signals
flow through successive latches rather than holding like registers will
do. Oh yes, the static timing analysis program is incapable of
calculating any timing analysis on them, so that is a real problem.

I have never needed a latch in any HDL design I have worked on. Do you
see a use for latches in your design?

--

Rick

 

[alb]

Hi Ron,

ronhk25 <ronhk25@gmail.com> wrote:

I always hear from FPGA designers that latches are "dangerous" and
that it's very important avoiding them.

What is 'dangerous' is not the latch in itself, rather the implicit
instantiation of a latch because of an incomplete assignment. This is
usually a sign something has been 'forgotten' by the designer, hence the
danger.

> I wonder what are the technical risks resulting by using latches.

AFAIK, timing analysis may have problems because it performs setup/hold
times verification based on clock propagation. If your enable signal is
slower than the data in your latch you'll have issues that are hard to
spot during timing analysis.

As far as I understand,
the main problem is that FPGAs don't have built in hard latches [...]

Not true, there are devices with built in latches (ex. ProAsic from
Microsemi) that are readily available even for automatic triplification
to enhance radiation tolerance.

I've never found the need to use a latch.

HTH,

Al