Disable Pull up

M

master

Guest
Someone knows like turn off the "pull up" that the family "spartan2"
connects for default to " tristate" placed inner lines in, from buffer "
Tbuf"?
I use "Xilinx ISE 4.1ě" and language "vhdl".
thanks
 
I don't sure to undestood your question but using the M0-M1-M2 pins is not
the right way to do what you want?

Regards
Giuseppe

"master" <ff@pla.it> ha scritto nel messaggio
news:iMM5b.292163$Ny5.9019956@twister2.libero.it...
Someone knows like turn off the "pull up" that the family "spartan2"
connects for default to " tristate" placed inner lines in, from buffer "
Tbuf"?
I use "Xilinx ISE 4.1ě" and language "vhdl".
thanks
Click to expand...
 
"Giuseppeł" <miaooaim@inwind.it> wrote in message news:<bj9a6r$gfbou$1@ID-61213.news.uni-berlin.de>...
I don't sure to undestood your question but using the M0-M1-M2 pins is not
the right way to do what you want?

Regards
Giuseppe

"master" <ff@pla.it> ha scritto nel messaggio
news:iMM5b.292163$Ny5.9019956@twister2.libero.it...
Someone knows like turn off the "pull up" that the family "spartan2"
connects for default to " tristate" placed inner lines in, from buffer "
Tbuf"?
I use "Xilinx ISE 4.1ě" and language "vhdl".
thanks
Click to expand...
excuse me for the little clear english.
I reformulate the question.

I use tool ise 4,1ě, family spartan2 and language vhdl . When I
synthetize a project that uses internal buffer tristate (tbuf), Pull
up component have been connected to buffer output for default. I would
want to disable this option and to put on the buffer output some pull
up or pull down to my choice. Does some environment variable or some
procedure exist in order to make that?

thanks
 
Master wrote:
"Giuseppeł" <miaooaim@inwind.it> wrote in message news:<bj9a6r$gfbou$1@ID-61213.news.uni-berlin.de>...

I don't sure to undestood your question but using the M0-M1-M2 pins is not
the right way to do what you want?

Regards
Giuseppe

"master" <ff@pla.it> ha scritto nel messaggio
news:iMM5b.292163$Ny5.9019956@twister2.libero.it...

Someone knows like turn off the "pull up" that the family "spartan2"
connects for default to " tristate" placed inner lines in, from buffer "
Tbuf"?
I use "Xilinx ISE 4.1ě" and language "vhdl".
thanks




excuse me for the little clear english.
I reformulate the question.

I use tool ise 4,1ě, family spartan2 and language vhdl . When I
synthetize a project that uses internal buffer tristate (tbuf), Pull
up component have been connected to buffer output for default. I would
want to disable this option and to put on the buffer output some pull
up or pull down to my choice. Does some environment variable or some
procedure exist in order to make that?

thanks
Click to expand...

- I don't like to insert directly pull-up in VHDL source file, because
pullups in the pads are technology dependant. But I put that in the UCF
file by :
############################
## PULL RESISTOR DESCRIPTION
############################
NET your_padname PULLUP ;
NET your_padname PULLDOWN ;

So, remove all pull-ups and pull-downs in your source file and add what
you need in the UCF.

Laurent Gauch
www.amontec.com
Your FPGA Design Partner
 
Master wrote:
"Giuseppeł" <miaooaim@inwind.it> wrote in message news:<bj9a6r$gfbou$1@ID-61213.news.uni-berlin.de>...

I don't sure to undestood your question but using the M0-M1-M2 pins is not
the right way to do what you want?

Regards
Giuseppe

"master" <ff@pla.it> ha scritto nel messaggio
news:iMM5b.292163$Ny5.9019956@twister2.libero.it...

Someone knows like turn off the "pull up" that the family "spartan2"
connects for default to " tristate" placed inner lines in, from buffer "
Tbuf"?
I use "Xilinx ISE 4.1ě" and language "vhdl".
thanks




excuse me for the little clear english.
I reformulate the question.

I use tool ise 4,1ě, family spartan2 and language vhdl . When I
synthetize a project that uses internal buffer tristate (tbuf), Pull
up component have been connected to buffer output for default. I would
want to disable this option and to put on the buffer output some pull
up or pull down to my choice. Does some environment variable or some
procedure exist in order to make that?

thanks
Click to expand...

- I don't like to insert directly pull-up in VHDL source file, because
pullups in the pads are technology dependant. But I put that in the UCF
file by :
############################
## PULL RESISTOR DESCRIPTION
############################
NET your_padname PULLUP ;
NET your_padname PULLDOWN ;

So, remove all pull-ups and pull-downs in your source file and add what
you need in the UCF.

Laurent Gauch
www.amontec.com
Your FPGA Design Partner
 
I use tool ise 4,1ě, family spartan2 and language vhdl . When I
synthetize a project that uses internal buffer tristate (tbuf), Pull
up component have been connected to buffer output for default. I would
want to disable this option and to put on the buffer output some pull
up or pull down to my choice. Does some environment variable or some
procedure exist in order to make that?

thanks
Click to expand...
Hi,

In Spartan-IIe Pull-up resistor on internal Tri-state net is
unavoidable as by documentation.
It should be the same in Spartan-II. Please correct me if it is wrong
or not the same.

Andrey
 
Spartan-II internal tristates are different than Spartan-II IOB tristates.

IOB tristates to the outside world have user programmable pullups.

Spartan-II internal tristates are tristate emulators, not actual tristate
lines. I'm having trouble finding the datasheet reference, but the behavior
is "like" there is a pullup with strong low drivers. When there are no
drivers, the state is high. When there are multiple drivers with
conflicting states, the part does not smoke but instead gives a logic low.
If you need a logic low when there are no drivers, either add the additional
circuitry to drive a logic low when no selects are active *or* invert the
logic so your re-inverted TBUF defaults to low when there are no drivers and
settles conflicts with a logic-high.


"Master" <fabrizio@planet1.it> wrote in message
news:d9da09be.0309050300.51dba2b2@posting.google.com...
"Giuseppeł" <miaooaim@inwind.it> wrote in message
news:<bj9a6r$gfbou$1@ID-61213.news.uni-berlin.de>...
I don't sure to undestood your question but using the M0-M1-M2 pins is
not
the right way to do what you want?

Regards
Giuseppe

"master" <ff@pla.it> ha scritto nel messaggio
news:iMM5b.292163$Ny5.9019956@twister2.libero.it...
Someone knows like turn off the "pull up" that the family "spartan2"
connects for default to " tristate" placed inner lines in, from buffer
"
Tbuf"?
I use "Xilinx ISE 4.1ě" and language "vhdl".
thanks



excuse me for the little clear english.
I reformulate the question.

I use tool ise 4,1ě, family spartan2 and language vhdl . When I
synthetize a project that uses internal buffer tristate (tbuf), Pull
up component have been connected to buffer output for default. I would
want to disable this option and to put on the buffer output some pull
up or pull down to my choice. Does some environment variable or some
procedure exist in order to make that?

thanks
Click to expand...
 
"John_H" <johnhandwork@mail.com> ha scritto nel messaggio
news:nK26b.35$X11.9145@news-west.eli.net...

If you need a logic low when there are no drivers, either
add the additional
circuitry to drive a logic low when no selects are active
*or* invert the
logic so your re-inverted TBUF defaults to low when there
are no drivers and
settles conflicts with a logic-high.
Click to expand...
What happens if you use VHDL's resolved signals (i.e. specifying at HDL
level the behaviour of bus conflicts)? It is automatically added
something like you described, or resolved signals are just for
simulation and don't work with "real" devices?

--
Lorenzo
 
I have invert logic of the buffer drive, but he is not changed null.
then I have realized a component that, when the buffer is in tristate
mode,it imposes the intentional level.it works correctly.

Regards
Fabrizio




"John_H" <johnhandwork@mail.com> wrote in message news:<nK26b.35$X11.9145@news-west.eli.net>...
Spartan-II internal tristates are different than Spartan-II IOB tristates.

IOB tristates to the outside world have user programmable pullups.

Spartan-II internal tristates are tristate emulators, not actual tristate
lines. I'm having trouble finding the datasheet reference, but the behavior
is "like" there is a pullup with strong low drivers. When there are no
drivers, the state is high. When there are multiple drivers with
conflicting states, the part does not smoke but instead gives a logic low.
If you need a logic low when there are no drivers, either add the additional
circuitry to drive a logic low when no selects are active *or* invert the
logic so your re-inverted TBUF defaults to low when there are no drivers and
settles conflicts with a logic-high.


"Master" <fabrizio@planet1.it> wrote in message
news:d9da09be.0309050300.51dba2b2@posting.google.com...
"Giuseppeł" <miaooaim@inwind.it> wrote in message
news:<bj9a6r$gfbou$1@ID-61213.news.uni-berlin.de>...
I don't sure to undestood your question but using the M0-M1-M2 pins is
not
the right way to do what you want?

Regards
Giuseppe

"master" <ff@pla.it> ha scritto nel messaggio
news:iMM5b.292163$Ny5.9019956@twister2.libero.it...
Someone knows like turn off the "pull up" that the family "spartan2"
connects for default to " tristate" placed inner lines in, from buffer
"
Tbuf"?
I use "Xilinx ISE 4.1ě" and language "vhdl".
thanks



excuse me for the little clear english.
I reformulate the question.

I use tool ise 4,1ě, family spartan2 and language vhdl . When I
synthetize a project that uses internal buffer tristate (tbuf), Pull
up component have been connected to buffer output for default. I would
want to disable this option and to put on the buffer output some pull
up or pull down to my choice. Does some environment variable or some
procedure exist in order to make that?

thanks
Click to expand...
 
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