Directly connect two XAUI ports inside FPGA

[Guenther Wenninger]

Hi all,

to implement something like a passthru mode, we want to directly
connect two XAUI ports inside the FPGA. The FPGA is a Xilinx Virtex-6.

Therefor we did instantiate two XAUI-cores and connected txd/txc from
one core with the rxd/rxc from the other core and vice versa.
Because both cores use a different refclk we simply added two
synchronizer FFs in between.

In our test-design this works. But when added to the full design
this code fails (the data after the synchronizer FFs seems scrambled).
Is it at all possible to directly connect two XAUI cores?
Is it possible to connect two blocks with the same clock frequency
but - probably - different clock phase just using 2xFFs?

Kind regards,
/gw

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For reply: Remove the additional chars from the local part.

 

[Tomas D.]

"Guenther Wenninger" <g!!rw@bitschubbser.org> wrote in message
news:slrnmja7fp.cf4.g!!rw@masterbase.bitschubbser.org...

Hi all,

to implement something like a passthru mode, we want to directly
connect two XAUI ports inside the FPGA. The FPGA is a Xilinx Virtex-6.

Therefor we did instantiate two XAUI-cores and connected txd/txc from
one core with the rxd/rxc from the other core and vice versa.
Because both cores use a different refclk we simply added two
synchronizer FFs in between.

In our test-design this works. But when added to the full design
this code fails (the data after the synchronizer FFs seems scrambled).
Is it at all possible to directly connect two XAUI cores?
Is it possible to connect two blocks with the same clock frequency
but - probably - different clock phase just using 2xFFs?

WHat about a DCFIFO and do transaction within packet boundary? E.g. transfer
to different clock domain (read fifo) when a full packet is in?

Regards
Tomas D.

 

[SysTom]

In the full design did the two XAUI ports use precisely the physical ports and internal routing?

 

[Guenther Wenninger]

Hi all,

thank you for the input. I also had the idea to use
a FIFO, but this needs some non-trivial glue-logic
as we want to dynamically change the connection mode
from "direct-connect" to "internal-data-to-xaui".

What I still would like to know: If it is "okay" to
synchronize two registered std_logic_vector's (same clock
frequency, different phase) using a 2-FF synchronizer.

What seems to have helped in the end was the AR from
Xilinx: http://www.xilinx.com/support/answers/39492.html

Thanks again and kind regards,
/gw

Guenther Wenninger <g!!rw@bitschubbser.org> schrieb:

Hi all,

to implement something like a passthru mode, we want to directly
connect two XAUI ports inside the FPGA. The FPGA is a Xilinx Virtex-6.

Therefor we did instantiate two XAUI-cores and connected txd/txc from
one core with the rxd/rxc from the other core and vice versa.
Because both cores use a different refclk we simply added two
synchronizer FFs in between.

In our test-design this works. But when added to the full design
this code fails (the data after the synchronizer FFs seems scrambled).
Is it at all possible to directly connect two XAUI cores?
Is it possible to connect two blocks with the same clock frequency
but - probably - different clock phase just using 2xFFs?

Kind regards,
/gw

--
For reply: Remove the additional chars from the local part.