Diploma work! To Create Schematic File from Netlist text fil

[Svenn Are Bjerkem]

On Nov 7, 7:45 am, lolita_l...@mail.ru wrote:

Hello,

I am a student of State Univercity of Moscow. I am writing Diploma
work .
I find these forum of Cadence company while searching the name of my
Diploma in Google.
I am not a member of Cadence Company .
I have to create Converter , which will convert ONLY digital standard
cells' netlist view into schematic file.
The input file is schematic netlist --- > for example some netlist of
NAND schema,with 3 inputs:

I II III IV V
mp1 sp1 A1 VDD VDD
mp2 sp1 A2 VDD VDD
mp3 Z sp1 VDD VDD
mn2 sn2 A2 VSS VSS
mn1 sp1 A1 sn2 VSS
mn3 Z sp1 VSS VSS

I : the names of NMOS and PMOS transistors, II: Drain connection ,
III: Gate connection, IV:Source , V: Bulk

From such discription of schematic the program which I am going to

create will generate transistor level schematic view (hierarchic or
flat (my choose)).As the work will be done only for standard digital

Hierarchy is always good as a brute-force flat placement will remove
about any information you could have gained by looking at a digital
design by hierarchy.

circuits , I think the view will be flat, as there is no hierarchi for
example in drawing Multiplexer.

Hi,
what Cadence version are you going to use? the IC6.x series have
SpiceIn to read in spice files if that is what you have as input.

I consider , the Cadence Tools are not open source , so I won't be
able to get access to them .

He, he, that is correct ....

I also try to get access to Spice Vision Pro program, it seems it does
such converting.

SpiceVision does a great job, but it is not that easy to get it
running. You have to do some manual work, but it pays off if you are
going to do this on a large netlist. You can even map the symbols of
your std. cells to already existing symbols from a cadence library, or
you can make your own. The default is rectangular boxes. *surprise*

Could you help , give any advise , how to start work of writing such
program!

Search in the documentation for info on functions like dbCreatePin,
dnCreateNet, dbCreateInst. You will find some programming examples on
how to use them.

Write a script in your favourite scripting language to parse the input
netlist (I had good luck with tcl and the graph package from tcllib)
to create a graph where your nodes are the subckts and your edges are
the instantiations and then add the pin interface as property to each
node and the interconnection as property to the edges. The output of
your script should be a valid SKILL program that you read into Cadence
with the load() command.

If you don't like to read documentation and want to know how it works
anyway, open an existing schematic and use the dbWriteSkill function
on the CIW command line to see how your script output should look
like.

Happy hacking,
--
Svenn

 

Hello,

I am a student of State Univercity of Moscow. I am writing Diploma
work .
I find these forum of Cadence company while searching the name of my
Diploma in Google.
I am not a member of Cadence Company .
I have to create Converter , which will convert ONLY digital standard
cells' netlist view into schematic file.
The input file is schematic netlist --- > for example some netlist of
NAND schema,with 3 inputs:

I II III IV V
mp1 sp1 A1 VDD VDD
mp2 sp1 A2 VDD VDD
mp3 Z sp1 VDD VDD
mn2 sn2 A2 VSS VSS
mn1 sp1 A1 sn2 VSS
mn3 Z sp1 VSS VSS

I : the names of NMOS and PMOS transistors, II: Drain connection ,
III: Gate connection, IV:Source , V: Bulk

From such discription of schematic the program which I am going to
create will generate transistor level schematic view (hierarchic or

flat (my choose)).As the work will be done only for standard digital
circuits , I think the view will be flat, as there is no hierarchi for
example in drawing Multiplexer.

I consider , the Cadence Tools are not open source , so I won't be
able to get access to them .
I also try to get access to Spice Vision Pro program, it seems it does
such converting.

Could you help , give any advise , how to start work of writing such
program!
Lola.

 

Hello Svenn ,

Can you tell my why people prefer to use spice vision over cadence spice in functionality?
Thanks
Govinda
On Wednesday, November 7, 2007 at 11:18:39 AM UTC-8, Svenn Are Bjerkem wrote:

On Nov 7, 7:45 am, lolita_l...@mail.ru wrote:
Hello,

I am a student of State Univercity of Moscow. I am writing Diploma
work .
I find these forum of Cadence company while searching the name of my
Diploma in Google.
I am not a member of Cadence Company .
I have to create Converter , which will convert ONLY digital standard
cells' netlist view into schematic file.
The input file is schematic netlist --- > for example some netlist of
NAND schema,with 3 inputs:

I II III IV V
mp1 sp1 A1 VDD VDD
mp2 sp1 A2 VDD VDD
mp3 Z sp1 VDD VDD
mn2 sn2 A2 VSS VSS
mn1 sp1 A1 sn2 VSS
mn3 Z sp1 VSS VSS

I : the names of NMOS and PMOS transistors, II: Drain connection ,
III: Gate connection, IV:Source , V: Bulk

From such discription of schematic the program which I am going to

create will generate transistor level schematic view (hierarchic or
flat (my choose)).As the work will be done only for standard digital

Hierarchy is always good as a brute-force flat placement will remove
about any information you could have gained by looking at a digital
design by hierarchy.

circuits , I think the view will be flat, as there is no hierarchi for
example in drawing Multiplexer.

Hi,
what Cadence version are you going to use? the IC6.x series have
SpiceIn to read in spice files if that is what you have as input.


I consider , the Cadence Tools are not open source , so I won't be
able to get access to them .

He, he, that is correct ....

I also try to get access to Spice Vision Pro program, it seems it does
such converting.

SpiceVision does a great job, but it is not that easy to get it
running. You have to do some manual work, but it pays off if you are
going to do this on a large netlist. You can even map the symbols of
your std. cells to already existing symbols from a cadence library, or
you can make your own. The default is rectangular boxes. *surprise*


Could you help , give any advise , how to start work of writing such
program!

Search in the documentation for info on functions like dbCreatePin,
dnCreateNet, dbCreateInst. You will find some programming examples on
how to use them.

Write a script in your favourite scripting language to parse the input
netlist (I had good luck with tcl and the graph package from tcllib)
to create a graph where your nodes are the subckts and your edges are
the instantiations and then add the pin interface as property to each
node and the interconnection as property to the edges. The output of
your script should be a valid SKILL program that you read into Cadence
with the load() command.

If you don't like to read documentation and want to know how it works
anyway, open an existing schematic and use the dbWriteSkill function
on the CIW command line to see how your script output should look
like.

Happy hacking,
--
Svenn