T
tachometer
Guest
Hi,
I have this project where I have to design a tachometer using VHDL. Th
thing is I m pretty new to the field of electronic projects and I m ver
new to VHDL.
The project asks me to count the Rotations/per Minute from a motor.
It has to be in the range 19-98 RPM, the measurement time is 1.1s, and th
display resolution is 0.1 .
The good part is that I dont have to create a system to get this rotations
they are given to me thru a generator. I just have to count the pulses an
display the result.
http://imageshack.us/photo/my-images/546/blockvk.jpg
So, I tought I'll use an AND gate with the signal from the general as on
input and the clock divided so I'll obtain the period of 1.1s .
http://imageshack.us/photo/my-images/839/clockbg.jpg/
What I have to do next is when i press a button it will count the pulse
for 1.1s and then display the result. [During counting the display will b
OFF].
Sorry for the long post but the first problem resumes to this. How do
design a clock divider so I can get a period of 1.1s.
I have a basic clock divider code where i count the rising edges and then
change the state of clock. But how many edges i have to count?
So : How do i get a clock with 0.909 freqvency from 50 MHZ internal cloc
of fpga?
[code:1:99554b0a89]ENTITY CLKDIV IS
PORT(
CLK: IN STD_LOGIC;
CLKOUT: OUT STD_LOGIC
);
END CLKDIV;
ARCHITECTURE DIV OF CLKDIV IS
BEGIN
PROCESS (CLK)
VARIABLE COUNT: INTEGER RANGE 0 TO ???? :=0;
VARIABLE STATE: STD_LOGIC := '1';
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(COUNT= )THEN
COUNT:=0;
STATE:= '1';
ELSE
COUNT := COUNT+1;
END IF;
IF(COUNT=)
STATE:= NOT STATE;
END IF;
END IF;
CLKOUT <= STATE;
END PROCESS;
END DIV;
[/code:1:99554b0a89]
---------------------------------------
Posted through http://www.FPGARelated.com
I have this project where I have to design a tachometer using VHDL. Th
thing is I m pretty new to the field of electronic projects and I m ver
new to VHDL.
The project asks me to count the Rotations/per Minute from a motor.
It has to be in the range 19-98 RPM, the measurement time is 1.1s, and th
display resolution is 0.1 .
The good part is that I dont have to create a system to get this rotations
they are given to me thru a generator. I just have to count the pulses an
display the result.
http://imageshack.us/photo/my-images/546/blockvk.jpg
So, I tought I'll use an AND gate with the signal from the general as on
input and the clock divided so I'll obtain the period of 1.1s .
http://imageshack.us/photo/my-images/839/clockbg.jpg/
What I have to do next is when i press a button it will count the pulse
for 1.1s and then display the result. [During counting the display will b
OFF].
Sorry for the long post but the first problem resumes to this. How do
design a clock divider so I can get a period of 1.1s.
I have a basic clock divider code where i count the rising edges and then
change the state of clock. But how many edges i have to count?
So : How do i get a clock with 0.909 freqvency from 50 MHZ internal cloc
of fpga?
[code:1:99554b0a89]ENTITY CLKDIV IS
PORT(
CLK: IN STD_LOGIC;
CLKOUT: OUT STD_LOGIC
);
END CLKDIV;
ARCHITECTURE DIV OF CLKDIV IS
BEGIN
PROCESS (CLK)
VARIABLE COUNT: INTEGER RANGE 0 TO ???? :=0;
VARIABLE STATE: STD_LOGIC := '1';
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(COUNT= )THEN
COUNT:=0;
STATE:= '1';
ELSE
COUNT := COUNT+1;
END IF;
IF(COUNT=)
STATE:= NOT STATE;
END IF;
END IF;
CLKOUT <= STATE;
END PROCESS;
END DIV;
[/code:1:99554b0a89]
---------------------------------------
Posted through http://www.FPGARelated.com