digital phase shift using synchronous design

S

Sachin Chandra

Guest
Hi all..
I am generating a phase shifted version of a single clock signal.
I had implemented a design which was kinda asynchronous in the sense
that the output of a flop was being used as a clock for the next flop
stage and so on thereby generating a ripple counter based design. The
design is perfect in the sense that there are no glitches and the
phase shift is done very well. But it poses a problem when using a
clock tree synthesis in that it becomes very complex and hence am
moving to a synchronous design wherein i use a single clock to
synchronize everything.
But since explicit delays like #5 etc cant be synthesized i was
wondering how to perform a digital phase shift of a clock signal. Well
a 180 degree phase shift can be produced with a single inversion but
the problem is in generating other phases like 90 degrees or 45 and so
on.
thanks in advance.

sachin
 
chandras20@hotmail.com (Sachin Chandra) wrote in message news:<2b3ac527.0401092144.5916f785@posting.google.com>...
Hi all..
I am generating a phase shifted version of a single clock signal.
I had implemented a design which was kinda asynchronous in the sense
that the output of a flop was being used as a clock for the next flop
stage and so on thereby generating a ripple counter based design. The
design is perfect in the sense that there are no glitches and the
phase shift is done very well. But it poses a problem when using a
clock tree synthesis in that it becomes very complex and hence am
moving to a synchronous design wherein i use a single clock to
synchronize everything.
But since explicit delays like #5 etc cant be synthesized i was
wondering how to perform a digital phase shift of a clock signal. Well
a 180 degree phase shift can be produced with a single inversion but
the problem is in generating other phases like 90 degrees or 45 and so
on.
thanks in advance.

sachin
Hi all..
Please ignore the earlier message on the phase shifting of clocks.
I managed to get it done using combinatorial logic generated after
observing the timing diagrams. I guess i had missed one of the
important rules of design and that is to observe the timing diagrams
carefully.
thanks
Sachin
 

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