Digital Design with just one clock at one edge

[Henning Bahr]

Hi there!
I hope this isn't too trivial:
I'm having a digital system with a finite state machine and a few
other modules which send a control signal to the FSM. Do you think it
is possible to use only clock and only posedge Flip Flops in such a
design? I can't manage it without the inverted clock so that the
control signals change at half the clock signal. But is there a way to
avoid this without violating setup and hold times?

Cheers,
Henning

 

[Mario Trams]

Henning Bahr wrote:

Hi there!
I hope this isn't too trivial:
I'm having a digital system with a finite state machine and a few
other modules which send a control signal to the FSM. Do you think it
is possible to use only clock and only posedge Flip Flops in such a
design? I can't manage it without the inverted clock so that the
control signals change at half the clock signal. But is there a way to
avoid this without violating setup and hold times?

I'm not completely sure, but I would say that today 90% of all clocked
designs are working with only one clock using only one edge.

What might scare you is your belief that the new state arrives
at the input of FlipFlops before the clock edge has "gone through",
right?

Indeed, that's a problem. But first it is to say that it takes some
time until the new state arrives. Secondly, clocked FlipFlops are
built so that they have a very narrow time margin for "opening".
This also requires more or less fast clock edges.
Thirdly, chip designers try to keep the clock skew at a minimum.
That is, all FlipFlops on the chip shall receive their clock
more or less at the same time. FPGAs (and ordinary chips as well)
have special clock distribution networks for this purpose.

To conclude: If you are working on an FPGA/CPLD design, you don't
need to worry about this issue and you can safely go with one clock
and one edge. The only thing you have to ensure is that you force
the clock signal to be routed via a clock distribution network.

Regards,
Mario

 

[Dan RADUT]

Henning.Bahr@ncl.ac.uk (Henning Bahr) wrote in message news:<8679149d.0307162201.49094c06@posting.google.com>...

Hi there!
I hope this isn't too trivial:
I'm having a digital system with a finite state machine and a few
other modules which send a control signal to the FSM. Do you think it
is possible to use only clock and only posedge Flip Flops in such a
design? I can't manage it without the inverted clock so that the
control signals change at half the clock signal. But is there a way to
avoid this without violating setup and hold times?

Cheers,
Henning

You can write your code using both the rising and falling edges of the clock.
All you need is to select a device(FPGA)that accomodates the clock frequency
and meets the timing constraints. Using timing constraints will help you to
implement(write) the VHDL code such as not to violate setup and hold times(in
Xilinx ISE is easy to do).

Regards,

DanR

 

[Peter Alfke]

Let me dig down to the bottom of this question:
Some designers worry that feeding data from one flip-flop output to the
input of another flip-flop clocked by the same clock is "dangerous",
since a late-arriving clock on the destination flip-flop might clock in
the already changed info from the first flip-flop. This is called a race
condition, or a hold-time violation.
The obvious cure to this "problem" is to alternate between rising and
falling clock edges. This "cure" works, but it creates unnecassary
complexity and cuts performance in half.
Our answer is: Don't worry, be happy! The chip designers have taken
care of this situation and given you a very fast, low-sekw clock
distribution net ( actually many of these flobal clock nets) that
completely eliminate the theoretical "problem".
But if you use normal routing resources to distribute the clock, then it
is wise to worry. Running the clock delays in the opposite direction of
the data flow is a well-known cure.

Peter Alfke, Xilinx
=====
Dan RADUT wrote:

Henning.Bahr@ncl.ac.uk (Henning Bahr) wrote in message news:<8679149d.0307162201.49094c06@posting.google.com>...
Hi there!
I hope this isn't too trivial:
I'm having a digital system with a finite state machine and a few
other modules which send a control signal to the FSM. Do you think it
is possible to use only clock and only posedge Flip Flops in such a
design? I can't manage it without the inverted clock so that the
control signals change at half the clock signal. But is there a way to
avoid this without violating setup and hold times?

Cheers,
Henning

You can write your code using both the rising and falling edges of the clock.
All you need is to select a device(FPGA)that accomodates the clock frequency
and meets the timing constraints. Using timing constraints will help you to
implement(write) the VHDL code such as not to violate setup and hold times(in
Xilinx ISE is easy to do).

Regards,

DanR

 

[Mike Treseler]

Peter Alfke wrote:

The obvious cure to this "problem" is to alternate between rising and
falling clock edges. This "cure" works, but it creates unnecassary
complexity and cuts performance in half.
Our answer is: Don't worry, be happy! The chip designers have taken
care of this situation and given you a very fast, low-skew clock
distribution net ( actually many of these flobal clock nets) that
completely eliminate the theoretical "problem".

I don't worry, and have been happy for a long time.
Having low-skew global nets is the upside of using FPGA's.

In cases where the falling edge seems to be needed to generate
narrower pulses, you can still be happy by using
the on-chip PLL/DLL to make and distribute a 2x clock.

-- Mike Treseler

 

[S. Ramirez]

"Henning Bahr" <Henning.Bahr@ncl.ac.uk> wrote in message
news:8679149d.0307162201.49094c06@posting.google.com...

Hi there!
I hope this isn't too trivial:
I'm having a digital system with a finite state machine and a few
other modules which send a control signal to the FSM. Do you think it
is possible to use only clock and only posedge Flip Flops in such a
design? I can't manage it without the inverted clock so that the
control signals change at half the clock signal. But is there a way to
avoid this without violating setup and hold times?

Cheers,
Henning

Henning,

I am assuming that the finite state machine and the "few other modules" are
all in the FPGA. It is very possible to do what you ask about, and it is
done day in and day out. As Peter Alfke said earlier, FPGAs are designed to
have the clock to out time be longer than the hold time, assuming the signal
propagated from Q to D input instantaneously. The only thing you have to
worry about is the sum of clock to Q time, routing time, setup time and
clock skew to be less than the clock period. That is what constraints are
for -- to tell the place and route tool to meet that timing and to quantify
it for you.

Now let's assume that you do use the opposite edge, i.e., falling edge, of
the clock. Also assume that you are not using a PLL or DLL. If the clock
is not guaranteed to be perfectly symmetrical, then you must do additional
analysis to determine what the high and low times are. You now need to
factor this timing in, using additional constraints, to determine just how
much time the tool should allow for the signal to make it to the opposite
edge, i.e., the rising edge of the flip flop. This complicates timing and
constraints, which detracts from the real task - to get a design working
efficiently in a minimal amount of time. There are reasons to use opposite
edges, but what you described above is not one of them.

What you have described above is a synchronous design with one clock domain.
Once you master a one clock design, you will be ready to move on to multiple
clock designs where circuitry can be grouped into clock domains. Then you
will have to learn how circuitry in one clock domain can talk reliably to
circuitry in another clock domain. There are special rules to achieve this
with great reliability, and it all comes under the heading of synchronous
design. From my experience, only a small percentage of companies have taken
the time and resources to document lessons learned (dating back to the
1970s) and generate design guides that cover this particular subject. These
companies covet their design guides and expect their engineers to use it
because they know it gives them a competitive edge. There are books,
though, that cover this topic. From my experience, the companies that have
not taken the time to document and generate design guides are also not
reading these books, because I see a fair amount of asynchronous design
usage, too.

Good luck to you.

Simon Ramirez, Consultant
Synchronous Design, Inc.
Oviedo, FL USA

 

[Peter Alfke]

The last sentence is important: You must route the clock using one of
the global clock distribution networks, with a clock skew below 100
picoseconds. Since the flip-flop response time ( clock-to-Q ) is longer
than this skew, there is no chance of any failure (race condition) due
to hold time violations.

Peter Alfke, Xilinx
====================
Mario Trams wrote:
<snip>

To conclude: If you are working on an FPGA/CPLD design, you don't
need to worry about this issue and you can safely go with one clock
and one edge. The only thing you have to ensure is that you force
the clock signal to be routed via a clock distribution network.

Regards,
Mario