Digital Clock Manager (DCM) Question

  • Thread starter David Joseph Bonnici
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David Joseph Bonnici

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Consider you have 100ppm crystal oscillator, 80ps jitter driving a DCM
that is configured to output x1.5 the input frequency. What will
happen to the jitter? Will it increase or decrease? And by what
factor?
 
The 100 ppm is irrelevant, it describes a constant frequency error.
The factor 1.5 is also irrelevant.
The output jitter will equal the input jitter plus about 50 ps coming
from the trim-tap uncertainty of the DCM.
Peter Alfke

David Joseph Bonnici wrote:
Consider you have 100ppm crystal oscillator, 80ps jitter driving a DCM
that is configured to output x1.5 the input frequency. What will
happen to the jitter? Will it increase or decrease? And by what
factor?
Click to expand...
 
I agree to 100ppm is irrelevant. But according to
http://www.xilinx.com/applications/web_ds_v2/jitter_calc.htm the factor does
matter.
I think you have to use the CLKFX output to multiply by 1.5, and the factor
is important. Or am I making a mistake, Peter?
Cheers, Syms.
"Peter Alfke" <peter@xilinx.com> wrote in message
news:40C74FC4.1ECD01C4@xilinx.com...
The 100 ppm is irrelevant, it describes a constant frequency error.
The factor 1.5 is also irrelevant.
The output jitter will equal the input jitter plus about 50 ps coming
from the trim-tap uncertainty of the DCM.
Peter Alfke
Click to expand...
 
All,

The 1.5 is important, but so is the origianl input frequency.

There is a jitter calculator used to calculate the jitter for any M, D
and input frequency.

For M=3, D=2, and F=100 MHz, the jitter (worst case noisy system)is 630
ps peak to peak (9.5% of a UI) for V2 Pro DCM.

Thus your timing slack for this clock domain has to be comfortably
better than 1/2 of 630 ps (to allow for the shortest possible period).

Austin

Symon wrote:
I agree to 100ppm is irrelevant. But according to
http://www.xilinx.com/applications/web_ds_v2/jitter_calc.htm the factor does
matter.
I think you have to use the CLKFX output to multiply by 1.5, and the factor
is important. Or am I making a mistake, Peter?
Cheers, Syms.
"Peter Alfke" <peter@xilinx.com> wrote in message
news:40C74FC4.1ECD01C4@xilinx.com...

The 100 ppm is irrelevant, it describes a constant frequency error.
The factor 1.5 is also irrelevant.
The output jitter will equal the input jitter plus about 50 ps coming
from the trim-tap uncertainty of the DCM.
Peter Alfke
Click to expand...
 
Hi Austin,
So, it's OK to assume the jitter is centred about the nominal ideal edge
position? I.e. Does the positive peak jitter equal the negative peak jitter?
Thanks, Syms.
"Austin Lesea" <austin@xilinx.com> wrote in message
news:ca7mpr$mov1@cliff.xsj.xilinx.com...
Thus your timing slack for this clock domain has to be comfortably
better than 1/2 of 630 ps (to allow for the shortest possible period).
Click to expand...
 
I stand corrected, very badly so. Sigh!
Peter Alfke

Peter Alfke wrote:
The 100 ppm is irrelevant, it describes a constant frequency error.
The factor 1.5 is also irrelevant.
The output jitter will equal the input jitter plus about 50 ps coming
from the trim-tap uncertainty of the DCM.
Peter Alfke

David Joseph Bonnici wrote:

Consider you have 100ppm crystal oscillator, 80ps jitter driving a DCM
that is configured to output x1.5 the input frequency. What will
happen to the jitter? Will it increase or decrease? And by what
factor?
Click to expand...
 
Symon,

Yes, it is.

In addition, its histogram is gaussian in shape (from the CLKFX) output.

Some folks have been really suprised that the jitter histogram is
gaussian in shape, but does not have the same RMS to peak to peak ratio
that is commonly assumed from a PLL (14 to 1), and yet it is still
random....(power spectral density has no peaks).

One can think of the output of the DCM as being multiple input clock
jitter histograms (which are usually very gaussian from crystal
oscillators), offset by a tap or two (at random + and -). Thus the peak
to peak vs RMS is closer to 4:1 or 6:1.

Austin

Symon wrote:
Hi Austin,
So, it's OK to assume the jitter is centred about the nominal ideal edge
position? I.e. Does the positive peak jitter equal the negative peak jitter?
Thanks, Syms.
"Austin Lesea" <austin@xilinx.com> wrote in message
news:ca7mpr$mov1@cliff.xsj.xilinx.com...

Thus your timing slack for this clock domain has to be comfortably
better than 1/2 of 630 ps (to allow for the shortest possible period).
Click to expand...
 
Peter,

Your answer is correct for the DLL outputs, CLK0, CLK90, CLK180, CLK270,
CLK2X, CLK2X_b, and CLKDV.

For example, if they had said "divided by 1.5" you are correct.

But not for CLKFX, and CLKFX_b.

7 out of 9 is not all that bad......

Also the 100ppm doesn't have anything at all to do with it.

I also forgot to add the square root of the sum of the squares (sqr
((630^2)+(80^2)) ~ 635 ps ) to get the total jitter out (clock + DCM).

Austin

Peter Alfke wrote:

I stand corrected, very badly so. Sigh!
Peter Alfke

Peter Alfke wrote:

The 100 ppm is irrelevant, it describes a constant frequency error.
The factor 1.5 is also irrelevant.
The output jitter will equal the input jitter plus about 50 ps coming
from the trim-tap uncertainty of the DCM.
Peter Alfke

David Joseph Bonnici wrote:

Consider you have 100ppm crystal oscillator, 80ps jitter driving a DCM
that is configured to output x1.5 the input frequency. What will
happen to the jitter? Will it increase or decrease? And by what
factor?
Click to expand...
 
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