diffrence between signal, variable and wire, register

[mohammed rafi]

hello every one

can you tell me the difrence between the data types signal, variable
in VHDL and wire, register in verilog?

Is wire a verilog equvalent of signal, similarly is register
equvalent to variable (in VHDL).

M. Rafi

 

[Steven Sharp]

m_mohammedrafi@yahoo.com (mohammed rafi) wrote in message news:<977f64b1.0405052126.e9f27e6@posting.google.com>...

Is wire a verilog equvalent of signal, similarly is register
equvalent to variable (in VHDL).

This is close to correct. However, Verilog allows sensitivity
or waiting on a register, while I don't believe VHDL allows
that for a variable. Also, I believe VHDL allows scheduling to
a signal in procedural code, with the process treated as a single
driver of the signal even though there may be multiple assignments
to the signal in the process. Verilog does not allow assigning
to a net (wire is only one type of net) in procedural code.

The basic distinction is in how the value is updated and resolved.
Different assignments to a net/signal (or different processes
assigning to a signal in VHDL) are treated as separate drivers of
the net/signal, which conceptually drive continuously. The effective
value is determined by resolving the values being driven. Assignments
to a variable or reg updates the effective value at a particular
time (generally when the procedural code containing the assignment
is executed), and has no lasting or continuous effect. The value
will be overwritten by the next assignment.

 

[mohammed rafi]

sharp@cadence.com (Steven Sharp) wrote in message news:<3a8e124e.0405060820.1e23a176@posting.google.com>...

m_mohammedrafi@yahoo.com (mohammed rafi) wrote in message news:<977f64b1.0405052126.e9f27e6@posting.google.com>...

Is wire a verilog equvalent of signal, similarly is register
equvalent to variable (in VHDL).

This is close to correct. However, Verilog allows sensitivity
or waiting on a register, while I don't believe VHDL allows
that for a variable. Also, I believe VHDL allows scheduling to
a signal in procedural code, with the process treated as a single
driver of the signal even though there may be multiple assignments
to the signal in the process. Verilog does not allow assigning
to a net (wire is only one type of net) in procedural code.

The basic distinction is in how the value is updated and resolved.
Different assignments to a net/signal (or different processes
assigning to a signal in VHDL) are treated as separate drivers of
the net/signal, which conceptually drive continuously. The effective
value is determined by resolving the values being driven. Assignments
to a variable or reg updates the effective value at a particular
time (generally when the procedural code containing the assignment
is executed), and has no lasting or continuous effect. The value
will be overwritten by the next assignment.

Thank you for clarifying my doubt.

Can you tell me when to use edge triggering in the event list of a
procedural statement and when to use level triggering

 

[Charles Bailey]

m_mohammedrafi@yahoo.com (mohammed rafi) wrote in message news:<977f64b1.0405052126.e9f27e6@posting.google.com>...

hello every one

can you tell me the difrence between the data types signal, variable
in VHDL and wire, register in verilog?

Is wire a verilog equvalent of signal, similarly is register
equvalent to variable (in VHDL).

M. Rafi

A Verilog wire is very similiar to a VHDL signal. One distinction is
that a wire cannot be set from an always block, which is similar to a
VHDL process.

In VHDL, every process that sets a signal is a driver and drives the
signal continuously. Unless a signal is supposed to be a tri-state
net, it should have only one driver. A concurrent signal assignment
statement, like
Y <= A and B;
is really a process, even if you didn't code it as such. (Modelsim
derives a process name based on the VHDL source code line number.) In
fact,
Y <= A and B;
is really just a shorthand way of coding
Line_nnn: Process (A, B)
Begin
Y <= A and B;
End Process;
The two are equivalent.

A Verilog reg is similar to a VHDL shared variable in the sense that
it can be set from more than one always block (or process in VHDL).
It differs from a shared variable in that it can hold delay
information and can trigger other events. A shared variable, on the
other hand, is similar to a named variable in a conventional
programming language and contains no delay information and cannot
trigger an event.