diffrence between declaring an o/p port as wire and declari

[mohammed rafi]

Hello everybody,
I cannot understand the diffrence between declaring the output port
of a module as wire and declaring the it as register. Please clarify
my doubt, and I also want to know at what situations we have to
declare the output port as register.

 

[Jim Wu]

I cannot understand the diffrence between declaring the output port
of a module as wire and declaring the it as register. Please clarify
my doubt, and I also want to know at what situations we have to
declare the output port as register.

If an output port is directly driven from an "always" block(combinatorial or
sequential), it needs to be defined as register. Otherwise, it's wire.

HTH,
Jim
jimwu88NOOOSPAM@yahoo.com
http://www.geocities.com/jimwu88/chips

 

[mohammed rafi]

"Jim Wu" <NOSPAM@NOSPAM.com> wrote in message news:<P8pmc.13535$vz5.11226@nwrdny01.gnilink.net>...

I cannot understand the diffrence between declaring the output port
of a module as wire and declaring the it as register. Please clarify
my doubt, and I also want to know at what situations we have to
declare the output port as register.

If an output port is directly driven from an "always" block(combinatorial or
sequential), it needs to be defined as register. Otherwise, it's wire.

HTH,
Jim
jimwu88NOOOSPAM@yahoo.com
http://www.geocities.com/jimwu88/chips

Thank you for replying.
Page number 52 in Verilog HDL by Samir Palnithkar says that " If
output ports hold their value they must be declared as reg", this was
the sentence that confused me so please tell me what the authour says
here.

 

[Jim Wu]

Page number 52 in Verilog HDL by Samir Palnithkar says that " If
output ports hold their value they must be declared as reg", this was
the sentence that confused me so please tell me what the authour says
here.

"reg" is a very confusing type in Verilog, at least to a hardware engineer
like me, because a reg doesn't necessarily map to a storage element in
hardware. IMO, the explanation in the book adds more confusion to it. The
definition of reg in the standard is more for simulation tool developers, I
guess.

The way I look at it that if a output port is driven from "always" block,
it has to be defined as "reg" (Simulation tools don't like it being defined
as "wire").

HTH,
Jim
jimwu88NOOOSPAM@yahoo.com
http://www.geocities.com/jimwu88/chips

 

[Steven Sharp]

m_mohammedrafi@yahoo.com (mohammed rafi) wrote in message news:<977f64b1.0405070209.54d87606@posting.google.com>...

Thank you for replying.
Page number 52 in Verilog HDL by Samir Palnithkar says that " If
output ports hold their value they must be declared as reg", this was
the sentence that confused me so please tell me what the authour says
here.

If you want to synthesize a sequential element (latch or flip-flop),
which holds a value, then you would need to use a reg. This would
be written to by an always block. This is presumably what the author
is referring to.

But this is not the only reason for using a reg. Sometimes purely
combinational logic is implemented using an always block, generally
to allow the use of procedural constructs like case statements. But
procedural code like always blocks can only write to regs/variables,
so that is what you have to use, even though there is no intent to
create a register.

An output port declared as a reg is effectively a local reg with
an implicit continuous assignment from the reg to a net that goes
out through the port. From outside the port, it doesn't make any
difference whether the port was declared internally as a reg or a
net; it is a net when it comes out.

 

[glen herrmannsfeldt]

Jim Wu wrote:

(snip)

"reg" is a very confusing type in Verilog, at least to a hardware engineer
like me, because a reg doesn't necessarily map to a storage element in
hardware. IMO, the explanation in the book adds more confusion to it. The
definition of reg in the standard is more for simulation tool developers, I
guess.

The way I look at it that if a output port is driven from "always" block,
it has to be defined as "reg" (Simulation tools don't like it being defined
as "wire").

To me, wires are used with continuous assignment statements,
such that they always have a value (continuously) assigned.

With an always statement, it is only assigned a value when the
condition is satisfied, and needs to keep its value, otherwise.

Personally, I prefer structural model over behavioral model,
in which case the usual use or reg is for registers.
(Which are behavioral model, but synthesizers know that.)

If, for example, a case construct is used to implement
a mux, it is, as far as varilog is concerned, only executed
when one of the signals changes. (For simulation, the
always condition should be correct.) The reg is what keeps
it constant when the inputs are not changing. (It makes more
sense from a simulation point of view, though.)

-- glen