Difficulty with OPB bus and user IP

[GpsBob]

Using the Memec MB1000 eval board with the Virtex-2 on it, I tried one
of the Memec projects "Lab06_Own_Periph_VirtexII1000". Building this
under the EDK 3.2 works fine on eval board. But, if I change line 163
of the file "opb_pwm_core.vhd" which reads:

SIn_DBus(I) <= '0';

to

SIn_DBus(I) <= '1';

which just changes the default output of the user IP, the system just
hangs after downloading the bitstream to the eval board. Any ideas?
Could there be some kind of contention within the OPB bus? I assume
that contentions are generally caught by the synthesis tools. If I
inspect the automatically generated vhdl, it seems that the bus
interfaces are generated correctly for the various peripherals tied to
the OPB bus. So, I'm at a loss as to why this is happening!

Bob


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[Ryan Laity]

Lasse Langwadt Christensen wrote:

GpsBob wrote:

Using the Memec MB1000 eval board with the Virtex-2 on it, I tried one
of the Memec projects "Lab06_Own_Periph_VirtexII1000". Building this
under the EDK 3.2 works fine on eval board. But, if I change line 163
of the file "opb_pwm_core.vhd" which reads:

SIn_DBus(I) <= '0';

to

SIn_DBus(I) <= '1';

which just changes the default output of the user IP, the system just
hangs after downloading the bitstream to the eval board. Any ideas?
Could there be some kind of contention within the OPB bus? I assume
that contentions are generally caught by the synthesis tools. If I
inspect the automatically generated vhdl, it seems that the bus
interfaces are generated correctly for the various peripherals tied to
the OPB bus. So, I'm at a loss as to why this is happening!

Bob



I've build SoC's where the muxing between IP-blocks were a big
OR, thus blocks that were inactive had to output zeros, if they
didn't the values read would be garbage. (it wouldn't create contention)

Don't know anything OPB, could it be that it is implemented the same
way?

-Lasse

Lasse, Bob:

I used that dreaded word (contention) far too loosely in my post; sorry
if I scared anyone.

Lasse, that is indeed how the OPB bus is built (an OR'd structure).
There will not be contention, there will be garbage data in Bob's case
if he drives a '1' onto the bus while another peripheral is trying to
drive a '0'.

Just as Lasse was implying, the reason the synthesis tool(s) will let
you do this is that from a hardware standpoint you're not doing anything
wrong by driving the bus with two peripherals since they're ORed.

Ryan Laity
Xilinx Applications