K
Kelvin
Guest
Hi, all:
In my 40MHz design, ISE failed to route a few wires in the end, with complaints on
timing violations also.
In fpga_editor, I could observe only a chunk of sinita/sinitb are green fly wires...When
I first core_gen-erated these block RAMs, I excluded sinita/sinitb...Why so special
about all these sinita/sinitbs?
Best Regards,
Kelvin
In my 40MHz design, ISE failed to route a few wires in the end, with complaints on
timing violations also.
In fpga_editor, I could observe only a chunk of sinita/sinitb are green fly wires...When
I first core_gen-erated these block RAMs, I excluded sinita/sinitb...Why so special
about all these sinita/sinitbs?
Best Regards,
Kelvin