Difficulty in programming from PROM

S

sam

Guest
Hello,
I am using a custom FPGA board with xC3S250e-vq100 from xilinx an
the PROM XCF04S. I am using Master serial mode configuration and i hav
permanently grounded M0,M1 and M2 mode select pins. I am using Platfor
Cable USB II for programming the FPGA. My board has 6 pin JTAG header whic
i connect to the Platform cable header. I am using Impact 12.4. The FPGA i
programmed properly when the bit file is downloaded directly to the FPG
and i get the proper output signals on the I/O's.
When PROM is programmed the message on impact says " Program Succeeded "
Given below is the console message.
'2': Loading file 'C:/Users/tsrc/Desktop/FPGA Boar
Test/fpgaboardtest/test.mcs' ...
done.
INFO:iMPACT - Current time: Sun Feb 13 16:15:37 2011
PROGRESS_START - Starting Operation.
Maximum TCK operating frequency for this device chain: 10000000.
Validating chain...
Boundary-scan chain validated successfully.
'2': Erasing device...
'2': Erasure completed successfully.
'2': Programming device...
done.
'2': Putting device in ISP mode...done.
'2': Putting device in ISP mode...done.
'2': Verifying device...done.
'2': Verification completed successfully.
'2': Calculated checksum matches expected checksum, 00568e386
'2': Putting device in ISP mode...done.
'2': Putting device in ISP mode...done.
'2': Setting user-programmable bits...
done.
'2': Putting device in ISP mode...done.
'2': Starting FPGA Load with Prom Data...INFO:iMPACT:563 - '2':pleas
ensure proper connections as specified by the data book ...
'2': Programming completed successfully.
'2': Programming completed successfully.
PROGRESS_END - End Operation.
Elapsed time = 14 sec.

The TCK speed was 6 MHz. Judging from the Console message i am guessing th
PROM is programmed correctly. But when i try to start up or pull down PRO
pin momentarily low the FPGA is not programmed. I do not get any outpu
signals on the I/O's. I did checked the DIN pin on FPGA using. When Starte
up or gave 0 on PROG pin using push button i saw the random bits which i a
guessing is configuration data. I also observed that the CCLK pin on th
FPGA is continuously giving out the clk pusles no matter what when the PRO
is programmed but goes off when only FPGA is programmed.

I have tried to follow the schematics from FPGA precisely but still have n
clue what is wrong.

Please help
Thanks!




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