Different Modelsim versions disagree in same backannotation!

[spectrallypure]

Hi all! I am experiencing a very strange and rather frustrating problem
while trying to run the same backannotated simulation in two different
versions of Modelsim. In both cases I am using exactly the very same
files for everything, and also the same compilation and simulation
commands. The old version (Modelsim 5.8b) simulates fine and gives the
expected results, while a newer release (Modelsim 6.2e) gives erroneous
results. The following caption explains the situation (copy and paste
the following link in your browser):

http://images.elektroda.net/5_1169063659.jpg

In the figure at the link above you can see the two simulations:

****[Upper part of image: Modelsim 5.8b - Results: OK, as expected]
Notice pulse on signal "RNet7947' begining @ 10263ns and falling @
10353ns. This is an update signal that is correctly fetched by the
clock "RNet7665" @ 10353ns. The good, expected behavior is that the
data in signal "WIR_shift" is updated to signal "PER/WIR", as shown.

****[Lower part of image: Modelsim 6.2b - Results: WRONG, unexpected]
Notice pulse on signal "RNet7947' this time begins @ 10264ns and falls
@ 10354ns, too early to be fetched by the clock "RNet7665" (see
carefully). Thus, the signal "WIR_shift" is NOT updated to signal
"PER/WIR", which remains in "000", as shown.

I would be the most grateful if anybody could please give a clue to
what is going wrong here. I REALLY need to get version 6.2e to run
correctly with my design. The simulation command issued in both
versions is as follows:
vsim -sdfmin /ram_16kx16_tap_top_tb_p1500/dfm_0=DFM_TC_Best.pt.sdf
-sdfnoerror -sdfnowarn -t ns +mindelays
work.ram_16kx16_tap_top_tb_p1500

In both cases I am using the same SDF file, with has the following
header:
(DELAYFILE
(SDFVERSION "OVI 3.0")
(DESIGN "DFM_TC")
(DATE "Fri Nov 24 16:01:11 2006")
(VENDOR "COREM10LPHVT CORXM10LPHVT IOLIB_65_M10_CUP_FT_TEST_1V2 PRM10
splpll_16Kx8")
(PROGRAM "Synopsys PrimeTime")
(VERSION "V-2003.12-SP1-3")
(DIVIDER /)
// OPERATING CONDITION "Best::Best"
(VOLTAGE 1.32::1.32)
(PROCESS "0.8000::0.8000")
(TEMPERATURE -40.00::-40.00)
(TIMESCALE 1ns)
....

Thanks in advance!!!
Regards, JL.

 

[Kim Enkovaara]

spectrallypure wrote:

#3 - Why are you set at 1ns resolution? Is this a *very* slow chip? I
bet your sim models are set to 1ps; I'd suspect a rounding problem somewhere.
We also think the problem might have to do with this. I just set the
resolution to 1ns because that is the value of the resolution of the
SDF files, but I have experimented by changing this value and the
timing of the waveform changes A LOT. However, I haven't been able to
make the simulation give the expected results by tweaking this
parameter. The operating frequency of the design is 50MHz.

You should set the resolution to what the models expect, nowadays the
resolution is usually 1ps or 10ps. The models can behave incorrectly
if the resolution is not correct.

And also the SDF must be generated from the layout tools with the same
or better resolution. 1ns resolution for the SDF files sounds very
large, unless you use some exotic or old process. Even for 0.13u process
1ps resolution is sometimes too high in STA.

#4 - What do you get if you enable sdf warnings & errors?

In 5.8b I get a lot (nearly 50,000) of the following warnings:

# ** Warning: (vsim-SDF-3262) ./DFM_TC_Worst.pt.sdf(<-SDF line number
here-&gt: Failed to find matching specify timing constraint.

... but the simulation works. On the other hand, in 6.2e, I get this
same error but a lot more times (something like three times more), I
additionally I get the following error (once again, I get it a lot of
times):

# ** Warning: (vsim-SDF-3261) ./DFM_TC_Worst.pt.sdf(<-SDF line number
here-&gt: Failed to find matching specify module path.

Normally you should not get any warnings or errors from the annotation.
They usually tell that the SDF is annotated to a wrong place or
simulation models do not match the synthesis models (library version
mismatch etc.). You should manually compare the SDF and the models to
see why the errors are there. I have seen usually warnings in special
analog cells, IO-testing structures etc. that are quite hard to model in
simulation.

50k errors is too much, <100 warnings for few gigabyte SDF sounds normal
figure. The tool might do things differently in error conditions
depending on versions.


--Kim