Different ifdef configurations in multiple instantiation

[Joe]

Hi all,

Got a small problem in my project but couldn't think of a good solution:
I've got a peripheral in verilog with ifdef statement to determine the
implementation. Now I need to instantiate multiple of the peripheral in
a project, and some of them use one configuration and some other use
another.

The obvious way is to rename the filenames and module names so that the
simulator can tell the different. But then it means I need to maintain
two copies of the same design. Is there any trick anyone know that can
solve this?

Thanks.
Joe

 

[Allan Herriman]

On Thu, 24 Jun 2004 09:07:38 +0100, Joe
<joe@very_silly_email_address.com> wrote:

Hi all,

Got a small problem in my project but couldn't think of a good solution:
I've got a peripheral in verilog with ifdef statement to determine the
implementation. Now I need to instantiate multiple of the peripheral in
a project, and some of them use one configuration and some other use
another.

The obvious way is to rename the filenames and module names so that the
simulator can tell the different. But then it means I need to maintain
two copies of the same design. Is there any trick anyone know that can
solve this?

This is a deficiency in earlier versions of Verilog that was fixed in
the 2001 language revision.

The generate and endgenerate keywords were added. Within them, you
can have if, for and case statements which get evaluated at
elaboration time and allow you to do what you want.

Notice that `ifdef, etc. get evaluated at compile time; generate if,
etc. get evaluated at elaboration time. This is an important
distinction.

e.g. This code instantiates N copies of my_component.

parameter N = ...;

wire [N-1:0] foo;

generate
genvar i;
for (i=0; i<N; i=i+1) begin : label1
my_component : label2 (
.foo(foo),
....
)
end
endgenerate


You can also do fun things with configurations.


Regards,
Allan.

 

[DW]

"Joe" <joe@very_silly_email_address.com> wrote in message
news:cbe1t2$lgn$1$8302bc10@news.demon.co.uk...

Hi all,

Got a small problem in my project but couldn't think of a good solution:
I've got a peripheral in verilog with ifdef statement to determine the
implementation. Now I need to instantiate multiple of the peripheral in
a project, and some of them use one configuration and some other use
another.

The obvious way is to rename the filenames and module names so that the
simulator can tell the different. But then it means I need to maintain
two copies of the same design. Is there any trick anyone know that can
solve this?

Thanks.
Joe
I used the "generate" statement which worked OK for me in both synthesis and

simulation. The following code could appear inside a "wrapper" module so
the interface to the outside world is the same regardless of internal
implementation.

parameter width=32;
parameter depth=64;

generate
if ((depth * width) < 256)
begin
module1 module_inst1(...);
defparam
module_inst1.width=width,
module_inst1.depth=depth;
end
else
begin
module2 module_inst2(...);
defparam
module_inst2.width=width,
module_inst2.depth=depth;
end
endgenerate

 

[Joe]

DW wrote:

"Joe" <joe@very_silly_email_address.com> wrote in message
news:cbe1t2$lgn$1$8302bc10@news.demon.co.uk...

Hi all,

Got a small problem in my project but couldn't think of a good solution:
I've got a peripheral in verilog with ifdef statement to determine the
implementation. Now I need to instantiate multiple of the peripheral in
a project, and some of them use one configuration and some other use
another.

The obvious way is to rename the filenames and module names so that the
simulator can tell the different. But then it means I need to maintain
two copies of the same design. Is there any trick anyone know that can
solve this?

Thanks.
Joe

I used the "generate" statement which worked OK for me in both synthesis and
simulation. The following code could appear inside a "wrapper" module so
the interface to the outside world is the same regardless of internal
implementation.

parameter width=32;
parameter depth=64;

generate
if ((depth * width) < 256)
begin
module1 module_inst1(...);
defparam
module_inst1.width=width,
module_inst1.depth=depth;
end
else
begin
module2 module_inst2(...);
defparam
module_inst2.width=width,
module_inst2.depth=depth;
end
endgenerate

Thanks guys.
But that means I need to completely re-code the peripheral block if I
use generate and parameters. (I don't have enough time to do that). So I
am wondering if I can compile the design twice using different
configuration in two separate library directories, and then during
simulation, loading the designs from both directories and specify which
instantiation use which implementation. (Like configuration in VHDL that
can specify different architecture of same module).

But then it will just be a 15 mins work to write a C-shell script to
rename filename and module names for each instantiation, which is some
how more attractive to me for the time being.
Cheers,
Joe

 

[Steven Sharp]

Joe <joe@very_silly_email_address.com> wrote in message news:<cbf8f0$c43$1$8302bc10@news.demon.co.uk>...

So I
am wondering if I can compile the design twice using different
configuration in two separate library directories, and then during
simulation, loading the designs from both directories and specify which
instantiation use which implementation. (Like configuration in VHDL that
can specify different architecture of same module).

Verilog-2001 added configurations, which allow binding different module
instances to different module definitions in different libraries.

However, I don't think Verilog configurations have been implemented as
widely in tools as generates have. You would have to check your tool
documentation to find out whether they are supported.

 

[Steven Sharp]

Joe <joe@very_silly_email_address.com> wrote in message news:<cbe1t2$lgn$1$8302bc10@news.demon.co.uk>...

The obvious way is to rename the filenames and module names so that the
simulator can tell the different. But then it means I need to maintain
two copies of the same design. Is there any trick anyone know that can
solve this?

You could use this obvious approach without the need to maintain two
copies of the same design. One way to do this would be to use an ifdef
around the module name in the declaration, so that you get two different
module names without having two copies of the module body. E.g.

module
`ifdef foo
modname1
`else
modname2
`endif
(port list here)
module body with more ifdefs
endmodule

Or if that is too ugly and you don't mind two copies of the port list,

`ifdef foo
modname1(port list here);
`else
modname2(port list here);
`endif
module body with more ifdefs
endmodule

Then compile the file twice with different -defines and you will get
two different module definitions.

Or put the module body into an include file and include it inside two
different module declarations.

module modname1
`define foo 0
`include "module_body.v"
endmodule

module modname2
`undef foo
`include "module_body.v"
endmodule

Sometimes the obvious approach is the best way to go.

 

[Joe]

Steven Sharp wrote:

Joe <joe@very_silly_email_address.com> wrote in message news:<cbe1t2$lgn$1$8302bc10@news.demon.co.uk>...

The obvious way is to rename the filenames and module names so that the
simulator can tell the different. But then it means I need to maintain
two copies of the same design. Is there any trick anyone know that can
solve this?


You could use this obvious approach without the need to maintain two
copies of the same design. One way to do this would be to use an ifdef
around the module name in the declaration, so that you get two different
module names without having two copies of the module body. E.g.

module
`ifdef foo
modname1
`else
modname2
`endif
(port list here)
module body with more ifdefs
endmodule

Or if that is too ugly and you don't mind two copies of the port list,

`ifdef foo
modname1(port list here);
`else
modname2(port list here);
`endif
module body with more ifdefs
endmodule

Then compile the file twice with different -defines and you will get
two different module definitions.

Or put the module body into an include file and include it inside two
different module declarations.

module modname1
`define foo 0
`include "module_body.v"
endmodule

module modname2
`undef foo
`include "module_body.v"
endmodule

Sometimes the obvious approach is the best way to go.

Thanks Steven.
I think I will go for the second method you suggest.
Seems quite easy to do.
Cheers!

Joe