Different ifdef configurations in multiple instantiation

[Joe]

Hi all,

Got a small problem in my project but couldn't think of a good solution:
I've got a peripheral in verilog with ifdef statement to determine the
implementation. Now I need to instantiate multiple of the peripheral in
a project, and some of them use one configuration and some other use
another.

The obvious way is to rename the filenames and module names so that the
simulator can tell the different. But then it means I need to maintain
two copies of the same design. Is there any trick anyone know that can
solve this?

Thanks.
Joe

 

[DW]

"Joe" <joe@very_silly_email_address.com> wrote in message
news:cbe1t2$lgn$1$8302bc10@news.demon.co.uk...

Hi all,

Got a small problem in my project but couldn't think of a good solution:
I've got a peripheral in verilog with ifdef statement to determine the
implementation. Now I need to instantiate multiple of the peripheral in
a project, and some of them use one configuration and some other use
another.

The obvious way is to rename the filenames and module names so that the
simulator can tell the different. But then it means I need to maintain
two copies of the same design. Is there any trick anyone know that can
solve this?

Thanks.
Joe
I used the "generate" statement which worked OK for me in both synthesis and

simulation. The following code could appear inside a "wrapper" module so
the interface to the outside world is the same regardless of internal
implementation.

parameter width=32;
parameter depth=64;

generate
if ((depth * width) < 256)
begin
module1 module_inst1(...);
defparam
module_inst1.width=width,
module_inst1.depth=depth;
end
else
begin
module2 module_inst2(...);
defparam
module_inst2.width=width,
module_inst2.depth=depth;
end
endgenerate

 

[Joe]

DW wrote:

"Joe" <joe@very_silly_email_address.com> wrote in message
news:cbe1t2$lgn$1$8302bc10@news.demon.co.uk...

Hi all,

Got a small problem in my project but couldn't think of a good solution:
I've got a peripheral in verilog with ifdef statement to determine the
implementation. Now I need to instantiate multiple of the peripheral in
a project, and some of them use one configuration and some other use
another.

The obvious way is to rename the filenames and module names so that the
simulator can tell the different. But then it means I need to maintain
two copies of the same design. Is there any trick anyone know that can
solve this?

Thanks.
Joe

I used the "generate" statement which worked OK for me in both synthesis and
simulation. The following code could appear inside a "wrapper" module so
the interface to the outside world is the same regardless of internal
implementation.

parameter width=32;
parameter depth=64;

generate
if ((depth * width) < 256)
begin
module1 module_inst1(...);
defparam
module_inst1.width=width,
module_inst1.depth=depth;
end
else
begin
module2 module_inst2(...);
defparam
module_inst2.width=width,
module_inst2.depth=depth;
end
endgenerate

Thanks guys.
But that means I need to completely re-code the peripheral block if I
use generate and parameters. (I don't have enough time to do that). So I
am wondering if I can compile the design twice using different
configuration in two separate library directories, and then during
simulation, loading the designs from both directories and specify which
instantiation use which implementation. (Like configuration in VHDL that
can specify different architecture of same module).

But then it will just be a 15 mins work to write a C-shell script to
rename filename and module names for each instantiation, which is some
how more attractive to me for the time being.
Cheers,
Joe