Differences in Verilog Coding for ASIC's and FPGAs

[rsk]

Dear friends,

Till now i had written verilog codes and targeted it to different
FPGA's.

But i had a doubt ,it is like this

what are the differences in verilog coding for FPGA'S and ASIC'S?And
what are the different ASIC libraries ?

Like
ASIC is having I/O pad so how do we declare those I/O pads in
verilog coding ,Such kind of things i want to know...

If you know any interesting website plz let me know...

I will be waiting for your reply...

Thankq

krs...

 

[glen herrmannsfeldt]

rsk wrote:

Till now i had written verilog codes and targeted it to different
FPGA's.

But i had a doubt ,it is like this

what are the differences in verilog coding for FPGA'S and ASIC'S?And
what are the different ASIC libraries ?

Like
ASIC is having I/O pad so how do we declare those I/O pads in
verilog coding ,Such kind of things i want to know...

FPGA's have I/O pads, which work just the same way. On all I
know, the ports for the top level module are pins.

The main difference between FPGA and ASIC is that you do much
more testing and simulation before sending the ASIC design out.

-- glen

 

[unfrostedpoptart]

Well, for every ASIC I've seen, you have to instantiate the I/O cells
in your design. For Xilinx FPGAs, I used to do this too. However, the
current recommended way for Xilinx and Altera is to imply the I/O
cells. Therefore, in the top level of your RTL, you would just have
inputs, outputs, and inouts.

Somewhere in the FPGA tool you would associate each of these ports with
an I/O type (e.g. TTL, LVDS), and a physical pad/pin location. I think
you can actually tell the FPGA tool the pin/type in the RTL via some
pragmas in the comment lines. I haven't tried this and don't know if
there's any cross-tool standard.

David

 

[MysticSage]

Glen is right.... almost

Normally there is no difference as far as RTL code is concerned. But
top level creation between ASIC and FPGA will be different. And that is
because of architectural/library difference between ASIC and FPGA. In
case of ASIC, GPIO, scan chain insertion, BIST etc may have to be
instantiated in top level. Otherwise current tools are smart enough to
aid design synthesis for ASIC or FPGA.

But for high performance/optimum FPGA design, it may be desirable to
micro-architect the design which is suitable (or make use of)
underlying FPGA architecture.

 

[J o h n _ E a t o n (at)]

MysticSage wrote:

But for high performance/optimum FPGA design, it may be desirable to
micro-architect the design which is suitable (or make use of)
underlying FPGA architecture.

Translation:

For high speed asic design you want to pipeline your design into as
many stages as you can get away with and seperate each one with enough
combinational logic to avoid hold time issues but not impact your clock
period.

For FPGA design you want to seperate all your flops with as much
combinational logic as you can fit into one of the fpga's LUT's
(logic lookup table). If you have a bunch of single gates or big
blocks needing multiple LUT's then your % of utilization goes
down.


John Eaton

 

[rsk]

Many thanks to all of you my dear friends.

when writing the verilog code which have to be targeted to fpga library
i will list my ports in inputs ,outputs and inouts in the same way can i
declare the i/o pads in inputs,outputs, or inouts?

and are there any asic families just like fpga families like
actel,atmel,altera,xilinx...?

thankq

rsk...

 

[glen herrmannsfeldt]

MysticSage wrote:

Glen is right.... almost

Normally there is no difference as far as RTL code is concerned. But
top level creation between ASIC and FPGA will be different. And that is
because of architectural/library difference between ASIC and FPGA. In
case of ASIC, GPIO, scan chain insertion, BIST etc may have to be
instantiated in top level. Otherwise current tools are smart enough to
aid design synthesis for ASIC or FPGA.

I suppose I would say those could be included in the testing
that I mentioned. Someone else mentioned pins. The software I
used to use had the option of automatic pin instantiation or
manual.

Scan chain is an interesting question, not normally used with
FPGAs. I don't know if ASIC tools will do that automatically.
It would seem better to do it during or after routing when you
know which FF are near which other ones.

But for high performance/optimum FPGA design, it may be desirable to
micro-architect the design which is suitable (or make use of)
underlying FPGA architecture.

Yes, the optimal design may be different, hopefully not too much
different.

-- glen

 

[John Penton]

rsk wrote:

Many thanks to all of you my dear friends.

when writing the verilog code which have to be targeted to fpga
library i will list my ports in inputs ,outputs and inouts in the
same way can i declare the i/o pads in inputs,outputs, or inouts?

and are there any asic families just like fpga families like
actel,atmel,altera,xilinx...?

Well, there are different process technologies, different cell libraries,
and different packages. These affect the cells available to you, their
characteristics, the amount of signal routing available (number of layers of
metal etc.), the number of pins available and various other things like how
much power you can get onto your IC. In general though, one piece of blank
silicon looks much like another - you are not limited to a finite number of
flops, just an amount of area to put them down on.

John

--
John Penton, posting as an individual unless specifically indicated
otherwise.