Differences between Xilinx ISE and Altera Quartus software

J

Jean Nicolle

Guest
Hi all,

I tried to summarize the differences in a table.
http://www.fpga4fun.com/table.html

Sorry about the link, it wasn't easy to duplicate the table in text form for
this posting.

Things I'd be interesting to hear about:
1. is the info accurate?
2. did I miss important features that differentiate the 2 software? (without
getting into details, these are big software...)

The table is intended as a beginner's guide to FPGA's software.
Thanks for any help/comments.
Jean
 
Jean Nicolle wrote:
Hi all,

I tried to summarize the differences in a table.
http://www.fpga4fun.com/table.html

Sorry about the link, it wasn't easy to duplicate the table in text form for
this posting.

Things I'd be interesting to hear about:
1. is the info accurate?
2. did I miss important features that differentiate the 2 software? (without
getting into details, these are big software...)

The table is intended as a beginner's guide to FPGA's software.
Thanks for any help/comments.
Jean
Click to expand...
Looks a good idea.

You could clarify that this is comparing FREE versions, with maybe
the cost of the first step upward from that ?.

Perhaps a Device Ceiling (Part num and appx resource ) ?
" Free up to XXXX "

Installed size (100's of MB ?), and machine minimums in MB RAM and GHz
clocks....

If you can be bothered, Links to a small code snippet for VHDL, verilog,
ABEL, AHDL could clarify that for beginners - something like a 4 bit
U/D/LD counter ?

-jg
 
"Jim Granville" <no.spam@designtools.co.nz> wrote in message
news:SXeTb.20077$ws.2691958@news02.tsnz.net...
Jean Nicolle wrote:
Hi all,

I tried to summarize the differences in a table.
http://www.fpga4fun.com/table.html

Sorry about the link, it wasn't easy to duplicate the table in text form
for
this posting.

Things I'd be interesting to hear about:
1. is the info accurate?
2. did I miss important features that differentiate the 2 software?
(without
getting into details, these are big software...)

The table is intended as a beginner's guide to FPGA's software.
Thanks for any help/comments.
Jean

Looks a good idea.

You could clarify that this is comparing FREE versions, with maybe
the cost of the first step upward from that ?.

Perhaps a Device Ceiling (Part num and appx resource ) ?
" Free up to XXXX "

Installed size (100's of MB ?), and machine minimums in MB RAM and GHz
clocks....
Click to expand...
I assume this is all for the Windows PC only. If so, what version(s) of the
OS are
supported - I believe Altera still supports Windows 98 and ME while Xilinx
requires
NT or XP. If not PC only, does it run on Linix? Not everybody, especially
those doing
things "for fun", have the latest OS versions. I ended up with Quartus
because I'm still
running 98SE.

If you can be bothered, Links to a small code snippet for VHDL, verilog,
ABEL, AHDL could clarify that for beginners - something like a 4 bit
U/D/LD counter ?

-jg
Click to expand...
 
Jean Nicolle <j.nicolle@sbcglobal.net> wrote:
: Hi all,

: I tried to summarize the differences in a table.
: http://www.fpga4fun.com/table.html

: Sorry about the link, it wasn't easy to duplicate the table in text form for
: this posting.

: Things I'd be interesting to hear about:
: 1. is the info accurate?
: 2. did I miss important features that differentiate the 2 software? (without
: getting into details, these are big software...)

: The table is intended as a beginner's guide to FPGA's software.
: Thanks for any help/comments.

You can use Iverilog for Xilinx too. And Cver also for both. Cver alos knows
about SDF and can be use for post layout simulation.

Bye

--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
 
You could clarify that this is comparing FREE versions, with maybe
the cost of the first step upward from that ?.
Actually the table is intended for both.
Click to expand...

Perhaps a Device Ceiling (Part num and appx resource ) ?
" Free up to XXXX "
Looks like the limit is 200KGates for Altera and 400KGates for Xilinx.
Click to expand...

Installed size (100's of MB ?), and machine minimums in MB RAM and GHz
clocks....
I'll look to see if there are big differences in the requirements. I could
Click to expand...
also include the OS'es supported

If you can be bothered, Links to a small code snippet for VHDL, verilog,
ABEL, AHDL could clarify that for beginners - something like a 4 bit
U/D/LD counter ?
Sounds like a good idea.
Click to expand...
 
You can use Iverilog for Xilinx too. And Cver also for both. Cver alos
knows
about SDF and can be use for post layout simulation.
Click to expand...
Sounds interesting.
Here, right?
http://www.pragmatic-c.com/commercial-cver/cver.htm

It doesn't seem available for free anymore though, even for non-commercial
use.
 
Do anyone knows the price of ISE/Quartus?
Do they come with the same scheme (1 year licencing)?
Once the license expires, does the software stops working, or there is just
no more updates?

Thanks.
 
Jean Nicolle wrote:
Hi all,

I tried to summarize the differences in a table.
http://www.fpga4fun.com/table.html

Sorry about the link, it wasn't easy to duplicate the table in text form for
this posting.

Things I'd be interesting to hear about:
1. is the info accurate?
2. did I miss important features that differentiate the 2 software? (without
getting into details, these are big software...)

The table is intended as a beginner's guide to FPGA's software.
Thanks for any help/comments.
Click to expand...
Thanks, that is great.
A minor note : AHDL is standing for Altera Highlevel language.
AFAIK, the free version only supports Megawizard function to
be output in AHDL.

Some pricetags would help too. The license restrictions would
also be of interest.
AFAIK, the Quartus2 free license is 90 or 180 days.

Rene
--
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net
 
Jean Nicolle <j.nicolle@sbcglobal.net> wrote:
: > You can use Iverilog for Xilinx too. And Cver also for both. Cver alos
: knows
: > about SDF and can be use for post layout simulation.

: Sounds interesting.
: Here, right?
: http://www.pragmatic-c.com/commercial-cver/cver.htm

: It doesn't seem available for free anymore though, even for non-commercial
: use.

There's a GPL-Cver version

--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
 
Rene Tschaggelar <none@none.net> wrote in message news:<a1a691870ee18d1408d46636e8d0500a@news.teranews.com>...
Jean Nicolle wrote:
Hi all,

I tried to summarize the differences in a table.
http://www.fpga4fun.com/table.html

Sorry about the link, it wasn't easy to duplicate the table in text form for
this posting.

Things I'd be interesting to hear about:
1. is the info accurate?
2. did I miss important features that differentiate the 2 software? (without
getting into details, these are big software...)

The table is intended as a beginner's guide to FPGA's software.
Thanks for any help/comments.

Thanks, that is great.
A minor note : AHDL is standing for Altera Highlevel language.
AFAIK, the free version only supports Megawizard function to
be output in AHDL.

Some pricetags would help too. The license restrictions would
also be of interest.
AFAIK, the Quartus2 free license is 90 or 180 days.

Rene
Click to expand...
Hi,

This is a correction to Rene's posting. The Quartus II 3.0 Web
Edition license duration is for 180 days, and can be renewed as many
times as needed from the web, i.e. there is no need to upgrade to a
full subscription at the end of the 180 days. The Megawizard Plug IN
Manager in the Quartus II 3.0 Web Edition provides output in VHDL,
Verilog and AHDL.


- Subroto Datta
Altera Corp.
 
Antti Lukats wrote:
Thanks, that is great.
A minor note : AHDL is standing for Altera Highlevel language.
AFAIK, the free version only supports Megawizard function to
be output in AHDL.

Some pricetags would help too. The license restrictions would
also be of interest.
AFAIK, the Quartus2 free license is 90 or 180 days.

Rene

Hi,

This is a correction to Rene's posting. The Quartus II 3.0 Web
Edition license duration is for 180 days, and can be renewed as many
times as needed from the web, i.e. there is no need to upgrade to a
full subscription at the end of the 180 days. The Megawizard Plug IN
Manager in the Quartus II 3.0 Web Edition provides output in VHDL,
Verilog and AHDL.

- Subroto Datta
Altera Corp.


Dear Altera Corp,

could you please also confirm is SOPC Builder that is bundled with Altera
Quartus II 3.0 Web Edition useable at all or not.

so far all our attempts todo something with it have failed:
NIOS is supplied (white icon?), after requesting NIOS evaluation license and
installing it, nothing changes, the NIOS in SOPC is not enabled.
and if there is no Avalon master then the SOPC doesnt do anything at all.
SOPC list DF6811 as Avalon master, so obtained eval license for DF6811 (from
provider DCD) - unfortunatly there is some problem as per DCD on Altera side
so DF6811 is not enabled in SOPC, so no way.
No Processor enabled, no avalon master no system can be built :(

I dont get it - if SOPC is included in free edition there should be
something that can be done with it ???

In previous versions of Altera free software I think the NIOS evaluation was
possible, unfortunatly I had very little time then and now this older
version probably would not recon the new license.

Ok, the long story short - is there any way to evaluate NIOS without paying
up front ?
Click to expand...

There at least were NIOS kits, meaning some FPGA, Stratix, or Cyclone hardware
together with a full license upgradeable withing a year to the latest version.
At around 450$ they were a bargain, considering the hardware.
You're never doing your own hardware for that little.

I wasn't able to run the kit due to configuration problems
and lack of time. So I cannot comment any further yet.

Rene
 
Rene Tschaggelar <none@none.net> writes:

Some pricetags would help too. The license restrictions would
Click to expand...
Xilinx ISE Foundation http://tinyurl.com/3745h
Altera Quartus II http://tinyurl.com/34ctk

Petter
--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?
 
cool, found it http://www.pragmatic-c.com/gpl-cver/
will add a link soon.
 
Thanks, that is great.
A minor note : AHDL is standing for Altera Highlevel language.
AFAIK, the free version only supports Megawizard function to
be output in AHDL.

Some pricetags would help too. The license restrictions would
also be of interest.
AFAIK, the Quartus2 free license is 90 or 180 days.

Rene

Hi,

This is a correction to Rene's posting. The Quartus II 3.0 Web
Edition license duration is for 180 days, and can be renewed as many
times as needed from the web, i.e. there is no need to upgrade to a
full subscription at the end of the 180 days. The Megawizard Plug IN
Manager in the Quartus II 3.0 Web Edition provides output in VHDL,
Verilog and AHDL.

- Subroto Datta
Altera Corp.
Click to expand...
Dear Altera Corp,

could you please also confirm is SOPC Builder that is bundled with Altera
Quartus II 3.0 Web Edition useable at all or not.

so far all our attempts todo something with it have failed:
NIOS is supplied (white icon?), after requesting NIOS evaluation license and
installing it, nothing changes, the NIOS in SOPC is not enabled.
and if there is no Avalon master then the SOPC doesnt do anything at all.
SOPC list DF6811 as Avalon master, so obtained eval license for DF6811 (from
provider DCD) - unfortunatly there is some problem as per DCD on Altera side
so DF6811 is not enabled in SOPC, so no way.
No Processor enabled, no avalon master no system can be built :(

I dont get it - if SOPC is included in free edition there should be
something that can be done with it ???

In previous versions of Altera free software I think the NIOS evaluation was
possible, unfortunatly I had very little time then and now this older
version probably would not recon the new license.

Ok, the long story short - is there any way to evaluate NIOS without paying
up front ?

Thanks
Antti Lukats
altera.openchip.org
 
[snip]
Ok, the long story short - is there any way to evaluate NIOS without
paying
up front ?


There at least were NIOS kits, meaning some FPGA, Stratix, or Cyclone
hardware
together with a full license upgradeable withing a year to the latest
version.
At around 450$ they were a bargain, considering the hardware.
You're never doing your own hardware for that little.

I wasn't able to run the kit due to configuration problems
and lack of time. So I cannot comment any further yet.
Click to expand...
Well, yes, I know there are kits at different price tags, but Altera says on
the website it is possible to evaluate NIOS without purchase (of NIOS or
eval kit). And if some Feature is included in some some software (like SOPC
Builder in Quartus Web Edition) then I guess it should be useable.
So I am still hoping that I am so stupid and cant figure it out how it can
be used. I started to write my own CPU for SOPC, but well it too much
trouble just to see if SOPC Builder does something or not. Hope somebody can
clear this up.
In case SOPC Builder is useable in evaluation mode only with 3rd party
processors (not NIOS) would be nice to know which ones are available and
working (the first one we tried turned out non-SOPC Builder ready, despite
its advertizing)

antti
 
Dear Altera Corp,

could you please also confirm is SOPC Builder that is bundled with Altera
Quartus II 3.0 Web Edition useable at all or not.

so far all our attempts todo something with it have failed:
NIOS is supplied (white icon?), after requesting NIOS evaluation license and
installing it, nothing changes, the NIOS in SOPC is not enabled.
and if there is no Avalon master then the SOPC doesnt do anything at all.
SOPC list DF6811 as Avalon master, so obtained eval license for DF6811 (from
provider DCD) - unfortunatly there is some problem as per DCD on Altera side
so DF6811 is not enabled in SOPC, so no way.
No Processor enabled, no avalon master no system can be built :(

I dont get it - if SOPC is included in free edition there should be
something that can be done with it ???

In previous versions of Altera free software I think the NIOS evaluation was
possible, unfortunatly I had very little time then and now this older
version probably would not recon the new license.

Ok, the long story short - is there any way to evaluate NIOS without paying
up front ?

Thanks
Antti Lukats
altera.openchip.org
Click to expand...

Hi Antti (and anyone else interested in the above question),

A colleague of mine answered this on your openchip web forum:

http://altera.openchip.org/forum/viewtopic.php?t=2#3&sid=070e4f3d938f67a4df77b9d249515feb

PS: The "white dots" in SOPC Builder show components that are
available elsewhere for download/CD, but not installed on your system.
There is a CD coming out shortly with an eval version of Nios. It will
be separate from the free Quartus download. Here is the link:
https://www.altera.com/literature/adl/adl-swtools.jsp

SOPC Builder is more of a design tool -- it did make its debut with
Nios and remains the main tool in the HW portion of a Nios design, but
there are many uses for it independent of Nios (for building
interconnects between user logic, downloading SOPC Builder components
from 3rd parties, using the Excalibur devices, etc.). This is why it
is installed automatically with Quartus now.

Jesse Kempa
Altera Corp.
jkempa at altera dot com
 
"Jean Nicolle" <j.nicolle@sbcglobal.net> wrote in message news:<YzeTb.20559$hv1.7139@newssvr25.news.prodigy.com>...
Hi all,

I tried to summarize the differences in a table.
http://www.fpga4fun.com/table.html

Sorry about the link, it wasn't easy to duplicate the table in text form for
this posting.

Things I'd be interesting to hear about:
1. is the info accurate?
2. did I miss important features that differentiate the 2 software? (without
getting into details, these are big software...)

The table is intended as a beginner's guide to FPGA's software.
Click to expand...
Ummmmmmmmmmmm...the most obvious, and perhaps most important
difference, is that Quartus only supports Altera parts, and Xilinx ISE
supports only Xilinx parts.

In other words, you choose the device based on whatever parameters you
care about, and then you get the software that lets you design the
chip. If only a Xilinx device has a gotta-have feature, it doesn't
matter if Altera's software is
cheaper/better/gets-you-a-good-raise/gets-you-laid (all of which may
or may not be true) because you can't use it for Xilinx parts.

--a
 
The table is now part of the site, see
http://www.fpga4fun.com/designsoftware.html
 
It looks fine except for functional/timing simulation.

Xilinx has MTI starter which is VHDL or Verilog, but only 500 lines of
code.
Altera has their own gate level simulator.
Both have issues, but it is unfair to just say NO for Xilinx and YES for Altera.

Peter Alfke, Xilinx
===========================

Jean Nicolle wrote:
The table is now part of the site, see
http://www.fpga4fun.com/designsoftware.html
Click to expand...
 
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