Difference between U, X and -

[Christian Christmann]

Hi,

what is the difference between these VHDL logic values:
U (uninitialized), X (1 and 0 combined) and - (don't care)?

Is for example U and X not the same, i.e. both values are
unknown?

Regards,
Chris

 

[KJ]

"Christian Christmann" <plfriko@yahoo.de> wrote in message
newsan.2007.03.02.09.56.03.149837@yahoo.de...

Hi,

what is the difference between these VHDL logic values:
U (uninitialized), X (1 and 0 combined) and - (don't care)?

Is for example U and X not the same, i.e. both values are
unknown?

When you're debugging some problem, it might be helpful to know that the

signal has never been set to anything ('U') or that there is at least one
process driving the signal to a '1' and another driving the same signal to a
'0' resulting in an 'X'. Other than that, whether you have a 'U' or an 'X'
in your design you 'usually' have a problem to fix. The reason it is only
'usually a problem' is because a signal that is at 'U' or 'X' in simulation
but never gets read by any process somewhat doesn't matter, since signals
that don't get read get optomized away during synthesis and simulations
aren't real. You're correct that 'U' and 'X' are both 'unknown' logic
states, the distinction between them is just a somewhat more detailed view
about why it is an unknown logic state.

The don't care value '-' is useful for synthesizable code in that you're
telling the synthesis tool that the value is not important (like for
example, the least few significant bits in an address bus when decoding an
address range). In simulation '-' is a little bit different. If you have
something like "if a = Some_Constant" where 'Some_Constant' has some '-'
embedded in it but the signal 'a' is a vector with only '0s' and '1s' in it
then the comparison will always fail because neither the '0' nor the '1'
will be equal to the '-' in those locations where 'Some_Constant' has them.
Instead you use the 'std_match(a, Some_Constant)' function. This function
will skip over the locations where there is a '-' and return a true value
when all of the other bits match, which is generally what you want it to do
and results in simulation and synthesis producing the same results whereas
using '=' might produce something where sim and synth results are different.

Kevin Jennings

 

[Ben Jones]

"Christian Christmann" <plfriko@yahoo.de> wrote in message
newsan.2007.03.02.09.56.03.149837@yahoo.de...

Hi,

what is the difference between these VHDL logic values:
U (uninitialized), X (1 and 0 combined) and - (don't care)?

Is for example U and X not the same, i.e. both values are
unknown?

The only difference is that they are different. You can use them for
whatever you like. They do not compare as equal to each other because they
are not.

Conventionally:

'X' means an undefined logic value due to e.g. bus contention or an invalid
situation (timing violation, etc).

'U' means an undefined logic value due to an uninitialised signal or
variable (i.e. no value assigned since the start of simulation);

'-' means "don't care"; you might use this in a truth-table context to
indicate that either a 1 or a 0 would be an acceptable output in some cases.
Synthesis tools vary in their support for this feature, though.

Cheers,

-Ben-