Difference between SV and SC

[Shreyas Kulkarni]

hi there,

what is the difference between SystemVerilog and SystemC?
both of them seem to me as being concerned with implementing C-like
structure in HDL domain.

to put it straight, are their developements ego-driven or really have
bigger and complementary differences, to be of any real use?

i dont't mean to hurt either followers of SV or SC, but things like
ego-driven developements do happen (u don't need me to tell this, do
u?).

regards,
Shreyas Kulkarni

 

[Swapnajit Mittra]

The difference between SystemVerilog and SystemC is
that the first is a language (that happens to be an
extension of an existing language), while the second
is an application specific library of an existing
language.

The answers to the rest of your questions can be
completely ego-driven, and hence, skipped here.

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