S
Sandhya
Guest
Hi,
Can anybody tell me what is difference between net and reg??when they are
supposed to use?
thanks
Can anybody tell me what is difference between net and reg??when they are
supposed to use?
thanks
Navigation
Install the app
How to install the app on iOS
Follow along with the video below to see how to install our site as a web app on your home screen.
Note: This feature may not be available in some browsers.
More options
You are using an out of date browser. It may not display this or other websites correctly.
You should upgrade or use an alternative browser.
You should upgrade or use an alternative browser.
J
Jonathan Bromley
Guest
"Sandhya" <spathak1212@yahoo.co.in> wrote in message
news:9b210cbd.0310142311.39fc1525@posting.google.com...
a good understanding of it before you move forward.
There are four big practical differences:
1) how to put a value onto a net or reg
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
* Registers get their values from procedural assignments,
in an "always" or "initial" block.
* Nets get their values from continuous assignment in one of
three ways:
- an explicit continuous "assign"
- by connecting the net to the output port of a module or
primitive instance
- by the net being an input port of the current module, and
that input port is driven from outside the module
2) what kind of values the net or reg can hold
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
* Each bit of a register holds a simple four-level 0/1/X/Z value.
* Each bit of a net carries a 0/1/X/Z value, but also has a
strength that is determined by the properties of its driver(s).
3) effect of multiple assignments
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
* You can make as many procedural assignments as you wish to
a register, from as many different "always" and "initial"
blocks as you wish. The register's value is determined
only by the most recent assignment to it. The effect of
any previous assignments is forgotten.
* You can have as many continuous assignments as you wish
to a net. Each of these continuous assignments has its
own driving value and its own driving strength. The
value seen on the net is the combined (resolved) effect
of all its drivers.
4) inertial and transport delay
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
* Nets exhibit inertial delay; registers can be assigned
with a transport delay. Perhaps someone else can come
up with a brief discussion of this?
My description is not 100% of the full story - there are
other issues, such as procedural "assign" and "force", that
have an effect - but if you understand my points (1) to (3)
properly, you won't go far wrong.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services
Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
news:9b210cbd.0310142311.39fc1525@posting.google.com...
This is an absolutely fundamental issue in Verilog and you MUST getCan anybody tell me what is difference between net and reg??when they are
supposed to use?
a good understanding of it before you move forward.
There are four big practical differences:
1) how to put a value onto a net or reg
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
* Registers get their values from procedural assignments,
in an "always" or "initial" block.
* Nets get their values from continuous assignment in one of
three ways:
- an explicit continuous "assign"
- by connecting the net to the output port of a module or
primitive instance
- by the net being an input port of the current module, and
that input port is driven from outside the module
2) what kind of values the net or reg can hold
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
* Each bit of a register holds a simple four-level 0/1/X/Z value.
* Each bit of a net carries a 0/1/X/Z value, but also has a
strength that is determined by the properties of its driver(s).
3) effect of multiple assignments
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
* You can make as many procedural assignments as you wish to
a register, from as many different "always" and "initial"
blocks as you wish. The register's value is determined
only by the most recent assignment to it. The effect of
any previous assignments is forgotten.
* You can have as many continuous assignments as you wish
to a net. Each of these continuous assignments has its
own driving value and its own driving strength. The
value seen on the net is the combined (resolved) effect
of all its drivers.
4) inertial and transport delay
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
* Nets exhibit inertial delay; registers can be assigned
with a transport delay. Perhaps someone else can come
up with a brief discussion of this?
My description is not 100% of the full story - there are
other issues, such as procedural "assign" and "force", that
have an effect - but if you understand my points (1) to (3)
properly, you won't go far wrong.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services
Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.