Difference between Generate-for and for

[Ethan Spitz]

Hi, I was wondering what the specific difference between a for loop used in generate and a for loop by itself in say a module is. Also, is genvar used only with generate, or can I use it with a by-itself for loop as its variable.

Thanks,
Ethan

 

[Kevin Neilson]

A loop in an 'always' block can do a lot of the same things a 'generate' loop can do. One major difference is that you can't instantiate blocks in a normal loop. Only the 'generate' loop allows you to control instantiation.

A 'generate' loop also adds levels of hierarchy, which a normal loop doesn't.

A genvar is only used with a 'generate' loop. With SystemVerilog, the 'generate' keyword can be omitted so the 'generate' loop looks like a normal loop sitting out by itself outside an always block:

for (genvar q=0; q<4; q++)
my_module(.clk(clk),.dout(dout));


The only way you can tell this is a 'generate' block is that it's off by itself (not inside an 'always' block), has a 'genvar' loop variable, and it instantiates a block.

 

[Mark Curry]

In article <92225d06-d81b-4dfe-b0d8-3470775337e9@googlegroups.com>,
Ethan Spitz <ethan.spitz@gmail.com> wrote:

Hi, I was wondering what the specific difference between a for loop
used in generate and a for loop by itself in say a module is. Also,
is genvar used only with generate, or can I
use it with a by-itself for loop as its variable.

Generate loops are evaluated at compile / elaboration time. NOT
at runtime. So the loops limits must be fully "known" at elaboration time.
You're just about unlimited as to what can go inside a generate loop.

Procedural 'for' loops are runtime evaluated as often as
neccesary when the procedural block is activated. They can be fully dynamic.
They MUST appear in a procedural block - thus have more limited use.

--Mark

 

[Jared Casper]

On 05/02/2013 01:00 AM, Ethan Spitz wrote:

Hi, I was wondering what the specific difference between a for loop used in generate and a for loop by itself in say a module is. Also, is genvar used only with generate, or can I use it with a by-itself for loop as its variable.

The generate keyword is optional. A for loop inside a
generate/endgenerate pair, and one without the generate/endgenerate pair
in the same place (inside a module but outside any procedural blocks)
are essentially the same thing. The only difference is the resulting
hierarchy.

A for loop not in a generate block (and not in a procedural block) is
still a loop generate construct and thus could use a genvar.

Jared

 

On Thursday, May 2, 2013 at 5:07:57 PM UTC-7, Mark Curry wrote:

Generate loops are evaluated at compile / elaboration time. NOT
at runtime. So the loops limits must be fully "known" at elaboration time.

Could this be thought of as a sort of "loop unrolling"?
https://en.wikipedia.org/wiki/Loop_unrolling

 

[rickman]

nmz787@gmail.com wrote on 8/14/2017 8:00 PM:

On Thursday, May 2, 2013 at 5:07:57 PM UTC-7, Mark Curry wrote:
Generate loops are evaluated at compile / elaboration time. NOT
at runtime. So the loops limits must be fully "known" at elaboration time.

Could this be thought of as a sort of "loop unrolling"?
https://en.wikipedia.org/wiki/Loop_unrolling

You can think of it as you wish, but it is very easy to understand if you
remember that Verilog is an HDL, Hardware Description Language. Just look
at what hardware might be generated by the statements of the loop and you
will see if it makes sense for "run time" execution. Anyway HDL code is not
really executed, it is compiled ultimately to hardware. Even in a simulator
it has to work the same way, so not really run time execution as much as it
is simulating what the hardware would do.

--

Rick C