K
Karl D
Guest
Press Release:
VDFsim: Fault simulator at the price of Logic simulator
Sunnyvale, CA (Oct. 13, 2003), DFTSimuLab, the supplier of high
performance and cost-effective simulation software introduces
its new family of fault simulators and logic simulators for Linux
and Unix based platforms.
The Verilog HDL compatible logic simulator, VDLsim, and concurrent
fault simulator, VDFsim, combine gate-level models with behavior-
level models to enable flexible scalability of simulation tasks
over design complexity.
The fault simulator supports a wide range of fault models including
standard stuck-at fault models and several bridging fault models
and accepts extended Verilog netlist representations. In addition,
the fault simulator supports several simulation algorithms and
is accurate over a wide range of timing models and circuit models
including gated clocks. Both event-driven and cycle-based evaluation
algorithms are supported for logic simulation as well as an application
interface, which enables users to compile behavioral-level module
descriptions in C and link directly into the simulation kernel.
The simulators provide a variety of useful verification and testability
checkers including feedback analysis, contention checking and toggle
coverage analysis. An interactive mode is available for structural
netlist analysis and for debug of simulation mismatches including
X tracing and logic cone analysis.
These products are the results of more than a decade of academic
research in the area of fault modeling, gate/switch-level simulation
and equivalence checking and many years of industrial experience in
DFT architecture and productization.
Pricing and availability:
Single site software licenses of VDFsim 2.2 can be purchased for
$500-$5,000 depending on simulator options.
Please visit our web site at www.dftsimulab.com for additional
information or send E-mail to dftsimulab@attbi.com
Contact person: Karl Dalen
VDFsim: Fault simulator at the price of Logic simulator
Sunnyvale, CA (Oct. 13, 2003), DFTSimuLab, the supplier of high
performance and cost-effective simulation software introduces
its new family of fault simulators and logic simulators for Linux
and Unix based platforms.
The Verilog HDL compatible logic simulator, VDLsim, and concurrent
fault simulator, VDFsim, combine gate-level models with behavior-
level models to enable flexible scalability of simulation tasks
over design complexity.
The fault simulator supports a wide range of fault models including
standard stuck-at fault models and several bridging fault models
and accepts extended Verilog netlist representations. In addition,
the fault simulator supports several simulation algorithms and
is accurate over a wide range of timing models and circuit models
including gated clocks. Both event-driven and cycle-based evaluation
algorithms are supported for logic simulation as well as an application
interface, which enables users to compile behavioral-level module
descriptions in C and link directly into the simulation kernel.
The simulators provide a variety of useful verification and testability
checkers including feedback analysis, contention checking and toggle
coverage analysis. An interactive mode is available for structural
netlist analysis and for debug of simulation mismatches including
X tracing and logic cone analysis.
These products are the results of more than a decade of academic
research in the area of fault modeling, gate/switch-level simulation
and equivalence checking and many years of industrial experience in
DFT architecture and productization.
Pricing and availability:
Single site software licenses of VDFsim 2.2 can be purchased for
$500-$5,000 depending on simulator options.
Please visit our web site at www.dftsimulab.com for additional
information or send E-mail to dftsimulab@attbi.com
Contact person: Karl Dalen