DFFR using DFF (only, may be extra gates)

Guest
Hi,

I know DFF is:

module DFF(d,clk,q) ;
input d, clk ;
output reg q ;

always @(posedge clk)
q<= d ;
endmodule

Now I need to implement ASYNCHRONOUS RESET flip flop
using DFF ONLY, may be some extract logic. HOW CAN I DO THAT ?

The implemented circuit MUST WORK AS FOLLOWS:

module DFFR(d,clk,r, q) ;
input d, clk,r ;
output reg q ;

always @(posedge clk or posedge r)
if (r) q <= 0 ;
else q<= d ;
endmodule

Please give the code or diagram. I am curious about this.

Sant
 
santhosh_h_98@yahoo.com wrote:
Hi,

I know DFF is:

module DFF(d,clk,q) ;
input d, clk ;
output reg q ;

always @(posedge clk)
q<= d ;
endmodule

Now I need to implement ASYNCHRONOUS RESET flip flop
using DFF ONLY, may be some extract logic. HOW CAN I DO THAT ?

The implemented circuit MUST WORK AS FOLLOWS:

module DFFR(d,clk,r, q) ;
input d, clk,r ;
output reg q ;

always @(posedge clk or posedge r)
if (r) q <= 0 ;
else q<= d ;
endmodule

Please give the code or diagram. I am curious about this.
Click to expand...
Well actually that'll cost logic in the clock path. You'll most likely
have to create an own clock clk_dffr which is clk or rst; and you'll
need d_dffr which will be d and not rst.

That should solve the task (though I'm not happy about that solution,
but no better one came to my mind).

Sant
Click to expand...
Regards,

Lorenz
 
On Dec 23, 11:54 am, Lorenz Kolb <lorenz.k...@uni-ulm.de> wrote:
santhosh_h...@yahoo.com wrote:
Hi,

I know DFF is:

module DFF(d,clk,q) ;
     input d, clk ;
     output reg q ;

     always @(posedge clk)
           q<= d ;
endmodule

Now I need to implement ASYNCHRONOUS RESET flip flop
using DFF ONLY, may be some extract logic. HOW CAN I DO THAT ?

The implemented circuit MUST WORK AS FOLLOWS:

module DFFR(d,clk,r, q) ;
     input d, clk,r ;
     output reg q ;

     always @(posedge clk or posedge r)
          if (r) q <= 0 ;
          else  q<= d ;
endmodule

Please give the code or diagram. I am curious about this.

Well actually that'll cost logic in the clock path. You'll most likely
have to create an own clock clk_dffr which is clk or rst; and you'll
need d_dffr which will be d and not rst.

That should solve the task (though I'm not happy about that solution,
but no better one came to my mind).

Sant

Regards,

Lorenz
Click to expand...
Even then you would need to ensure adequate setup time on the D
input when resetting. Assuming D was otherwise high, d_dffr and
clk_dffr would change at the same time unless you made extra delay
in the clock path. And of course you need to make sure that
your path from the standard D input still has hold time after
all of the gating...

Good luck,
Gabor
 
Now I need to implement ASYNCHRONOUS RESET flip flop
using DFF ONLY, may be some extract logic. HOW CAN I DO THAT ?

The implemented circuit MUST WORK AS FOLLOWS:

module DFFR(d,clk,r, q) ;
     input d, clk,r ;
     output reg q ;

     always @(posedge clk or posedge r)
          if (r) q <= 0 ;
          else  q<= d ;
endmodule

Please give the code or diagram. I am curious about this.
Click to expand...
The thing I'm curious about is WHY?

Gabor is right about the extreme difficulty of getting
something that works correctly if you try to gate reset
and clock together.

If you're allowed any amount of combinational logic
in addition to DFF, which I assume is the case, then
you could consider this idea, (c)2008 Santa's Elves,
to be enjoyed in moderation with a vomit-bag handy:

module DFFR(input d, clk, r, output q);
//
wire d_int, q_int, flipper;
//
// Here's the main FF. Its output is inverted
// if necessary to give reset behaviour.
DFF data_ff(.d(d_int), .clk(clk), .q(q_int));
assign q = q_int ^ flipper;
//
// The second FF captures the data FF's output
// when reset happens, and uses that captured
// value to invert the main FF's output if necessary.
DFF flipper_ff(.d(q_int), .clk(r), .q(flipper);
//
// Finally, we invert the D input to the main FF
// to match the inversion of its output. But we
// also disable clocking of this FF while reset
// is active, so that we don't need to worry about
// the reset value at any time other than (posedge r).
assign d_int = r? q_int: d ^ flipper;
//
endmodule

This is still exposed to a race between active edges
of clock and reset, but otherwise I think it works;
and it doesn't corrupt the hold time behaviour of the
main (data_ff) flop.

Actually, on mature reflection I think this one is
(c)2008 The Grinch.

Season's Greetings to all :)
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
I
Gabor is right about the extreme difficulty of getting
something that works correctly if you try to gate reset
and clock together.

If you're allowed any amount of combinational logic
in addition to DFF, which I assume is the case, then
you could consider this idea, (c)2008 Santa's Elves,
to be enjoyed in moderation with a vomit-bag handy:
Click to expand...
If you have unlimited gates, why not just ignore the DFF?

Old data books gave gate level diagrams for things
like FFs. Here is an example:
http://focus.ti.com/lit/ds/symlink/sn74ls74a.pdf

An edge triggered FF is two latches. A latch is
a pair of cross coupled gates. Set/Reset are just
another term into some of the gates.

--
These are my opinions, not necessarily my employer's. I hate spam.
 
On Dec 23, 1:20 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
Now I need to implement ASYNCHRONOUS RESET flip flop
using DFF ONLY, may be some extract logic. HOW CAN I DO THAT ?

The implemented circuit MUST WORK AS FOLLOWS:

module DFFR(d,clk,r, q) ;
     input d, clk,r ;
     output reg q ;

     always @(posedge clk or posedge r)
          if (r) q <= 0 ;
          else  q<= d ;
endmodule

Please give the code or diagram. I am curious about this.

The thing I'm curious about is WHY?

Gabor is right about the extreme difficulty of getting
something that works correctly if you try to gate reset
and clock together.

If you're allowed any amount of combinational logic
in addition to DFF, which I assume is the case, then
you could consider this idea, (c)2008 Santa's Elves,
to be enjoyed in moderation with a vomit-bag handy:

module DFFR(input d, clk, r, output q);
  //
  wire d_int, q_int, flipper;
  //
  // Here's the main FF.  Its output is inverted
  // if necessary to give reset behaviour.
  DFF data_ff(.d(d_int), .clk(clk), .q(q_int));
  assign q = q_int ^ flipper;
  //
  // The second FF captures the data FF's output
  // when reset happens, and uses that captured
  // value to invert the main FF's output if necessary.
  DFF flipper_ff(.d(q_int), .clk(r), .q(flipper);
  //
  // Finally, we invert the D input to the main FF
  // to match the inversion of its output.  But we
  // also disable clocking of this FF while reset
  // is active, so that we don't need to worry about
  // the reset value at any time other than (posedge r).
  assign d_int = r? q_int: d ^ flipper;
  //
endmodule

This is still exposed to a race between active edges
of clock and reset, but otherwise I think it works;
and it doesn't corrupt the hold time behaviour of the
main (data_ff) flop.

Actually, on mature reflection I think this one is
(c)2008 The Grinch.

Season's Greetings to all :)
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Click to expand...
Wow! My head is spinning!

It seems to me if you want to use the gated Q approach, you
don't really need a "flipper" but only an AND gate since
reset can only drive the Q output low. If you made an
internal reset signal, on while "r" is asserted and
held until the data flip-flop Q output is low, you can
gate this into the d input of the data flip-flop as
a synchronous reset, and also gate it with Q to make the
reset appear asynchronous. You wouldn't need a proper
D flip-flop for the reset signal, just an implied
latch like:

r_int = r | r_int & q_int;

then

d_int = d & !r_int;

q = q_int & !r_int;

Cheers,
Gabor
 
On Tue, 23 Dec 2008 18:20:50 +0000, Jonathan Bromley
<jonathan.bromley@MYCOMPANY.com> wrote:

This is still exposed to a race between active edges
of clock and reset, but otherwise I think it works;
and it doesn't corrupt the hold time behaviour of the
main (data_ff) flop.
Click to expand...
How is this any different from a DFFR ie a DFF with built-in async
reset? One has to meet the reset removal timing in a DFFR which is the
same problem with your solution above.

Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services
http://www.dspia.com
 
On Tue, 23 Dec 2008 11:12:45 -0800 (PST), gabor <gabor@alacron.com>
wrote:

It seems to me if you want to use the gated Q approach, you
don't really need a "flipper" but only an AND gate since
reset can only drive the Q output low. If you made an
internal reset signal, on while "r" is asserted and
held until the data flip-flop Q output is low, you can
gate this into the d input of the data flip-flop as
a synchronous reset, and also gate it with Q to make the
reset appear asynchronous. You wouldn't need a proper
D flip-flop for the reset signal, just an implied
latch like:

r_int = r | r_int & q_int;

then

d_int = d & !r_int;

q = q_int & !r_int;
Click to expand...
This doesn't solve the problem perfectly. A real async reset flop
doesn't need a clock edge to reset the internal state of the flop so
if a reset arrives and leaves before any clock edges appear the Q of
the flop changes to and stays at 0. In the case above the you have no
control over q_int which is presumably X in this condition so when you
remove reset q will go back to X which is what the async reset was
trying to solve after all.

Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services
http://www.dspia.com
 
On Dec 23, 3:25 pm, Muzaffer Kal <k...@dspia.com> wrote:
On Tue, 23 Dec 2008 11:12:45 -0800 (PST), gabor <ga...@alacron.com
wrote:



It seems to me if you want to use the gated Q approach, you
don't really need a "flipper" but only an AND gate since
reset can only drive the Q output low.  If you made an
internal reset signal, on while "r" is asserted and
held until the data flip-flop Q output is low, you can
gate this into the d input of the data flip-flop as
a synchronous reset, and also gate it with Q to make the
reset appear asynchronous.  You wouldn't need a proper
D flip-flop for the reset signal, just an implied
latch like:

r_int = r | r_int & q_int;

then

d_int = d & !r_int;

q = q_int & !r_int;

This doesn't solve the problem perfectly. A real async reset flop
doesn't need a clock edge to reset the internal state of the flop so
if a reset arrives and leaves before any clock edges appear the Q of
the flop changes to and stays at 0. In the case above the you have no
control over q_int which is presumably X in this condition so when you
remove reset q will go back to X which is what the async reset was
trying to solve after all.

Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Serviceshttp://www.dspia.com
Click to expand...
Well actually that is why r_int is held until q_int goes
low. This guarantees that the next clock edge after reset
also clocks the Q low. The down side to this of course
is that it doesn't actually model a D flip-flop with
async reset, which could possibly go high on the first
edge after reset is released.
 
On Tue, 23 Dec 2008 12:46:45 -0800 (PST), Gabor <gabor@alacron.com>
wrote:
On Dec 23, 3:25 pm, Muzaffer Kal <k...@dspia.com> wrote:
On Tue, 23 Dec 2008 11:12:45 -0800 (PST), gabor <ga...@alacron.com
wrote:



It seems to me if you want to use the gated Q approach, you
don't really need a "flipper" but only an AND gate since
reset can only drive the Q output low.  If you made an
internal reset signal, on while "r" is asserted and
held until the data flip-flop Q output is low, you can
gate this into the d input of the data flip-flop as
a synchronous reset, and also gate it with Q to make the
reset appear asynchronous.  You wouldn't need a proper
D flip-flop for the reset signal, just an implied
latch like:

r_int = r | r_int & q_int;

then

d_int = d & !r_int;

q = q_int & !r_int;

This doesn't solve the problem perfectly. A real async reset flop
doesn't need a clock edge to reset the internal state of the flop so
if a reset arrives and leaves before any clock edges appear the Q of
the flop changes to and stays at 0. In the case above the you have no
control over q_int which is presumably X in this condition so when you
remove reset q will go back to X which is what the async reset was
trying to solve after all.

Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services
http://www.dspia.com

Well actually that is why r_int is held until q_int goes
low. This guarantees that the next clock edge after reset
also clocks the Q low. The down side to this of course
is that it doesn't actually model a D flip-flop with
async reset, which could possibly go high on the first
edge after reset is released.
Click to expand...
I think the down side is a little more than that. If q_int is X (which
is what one should expect for a flop with no async controls),
"r_int & q_int" is also X. So when r goes high then low, r_int is 1
then X. I don't think you're getting the latching affect you're
looking for; in Verilog simulation anyway.
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services
http://www.dspia.com
 
On Tue, 23 Dec 2008 12:19:34 -0800, Muzaffer Kal <kal@dspia.com>
wrote:

On Tue, 23 Dec 2008 18:20:50 +0000, Jonathan Bromley wrote:

This
Click to expand...
[...devil's-spawn I proposed for a DFFR made only from
DFFs and gates]

is still exposed to a race between active edges
of clock and reset

How is this any different from a DFFR ie a DFF with built-in async
reset? One has to meet the reset removal timing in a DFFR which is the
same problem with your solution above.
Click to expand...
The problem isn't removal/recovery. It's at the *assertion*
of reset, when the "flipper" DFF captures the current state
of the data FF. If the data FF changes state at the same
time, thanks to a simultaneous clock edge, the flipper can
hold the wrong value and the whole mess might reset to 1
instead of 0. A conventional DFFR model doesn't suffer
from such a race, and nor does the real thing.

It's easy to fix by introducing a non-zero time delay in
the clock path to the flipper DFF's clock. But then the
whole thing could fail if there's a reset pulse shorter
than that time delay. I don't think there is any way out
that is completely bombproof.

Of course, as someone else pointed out, you can do the whole
thing with a gate-level model of a master-slave flip-flop,
or something similar. I didn't feel that was in the spirit
of the original rather bizarre question, so provided instead
my correspondingly bizarre solution. I still think it goes
rather well with the mince pies, plum pudding and other
general Yuletide excesses:
On the first day of Christmas my client sent to me
a skew-ridden gated clock tree.
On the second day of Christmas my client sent to me
two setup failures and a skew-ridden gated clock tree.
On the third day....
bah, humbug, you get the general idea.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
On Tue, 23 Dec 2008 22:46:22 +0000, Jonathan Bromley
<jonathan.bromley@MYCOMPANY.com> wrote:

On Tue, 23 Dec 2008 12:19:34 -0800, Muzaffer Kal <kal@dspia.com
wrote:

On Tue, 23 Dec 2008 18:20:50 +0000, Jonathan Bromley wrote:

This

[...devil's-spawn I proposed for a DFFR made only from
DFFs and gates]

is still exposed to a race between active edges
of clock and reset

How is this any different from a DFFR ie a DFF with built-in async
reset? One has to meet the reset removal timing in a DFFR which is the
same problem with your solution above.

The problem isn't removal/recovery. It's at the *assertion*
of reset, when the "flipper" DFF captures the current state
of the data FF. If the data FF changes state at the same
time, thanks to a simultaneous clock edge, the flipper can
hold the wrong value and the whole mess might reset to 1
instead of 0. A conventional DFFR model doesn't suffer
from such a race, and nor does the real thing.
Click to expand...
Actually I think there is another issue with the model. It is possible
that the reset will start high at the start of the simulation and
there won't be a posedge for the flipper flop to see. I am not sure if
the model handles that case correctly.

Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services
http://www.dspia.com
 
On 23 Dez., 13:57, santhosh_h...@yahoo.com wrote:
Now I need to implement ASYNCHRONOUS RESET flip flop
using DFF ONLY, may be some extract logic. HOW CAN I DO THAT ?
Click to expand...
Impossible without additional logic.
If you need to use additional logic, why bother about dff?
Assume you have really a technology with only dff as clocked gates,
you could still use pure logic (picked from a book in your high
school) as in the old days when you need to build your ff as a
bistable multivibrator and forget the dff. I think this saves you from
a lot of trouble

bye Thomas
 
santhosh_h_98@yahoo.com wrote:
Hi,

I know DFF is:

module DFF(d,clk,q) ;
input d, clk ;
output reg q ;

always @(posedge clk)
q<= d ;
endmodule

Now I need to implement ASYNCHRONOUS RESET flip flop
using DFF ONLY, may be some extract logic. HOW CAN I DO THAT ?

The implemented circuit MUST WORK AS FOLLOWS:

module DFFR(d,clk,r, q) ;
input d, clk,r ;
output reg q ;

always @(posedge clk or posedge r)
if (r) q <= 0 ;
else q<= d ;
endmodule

Please give the code or diagram. I am curious about this.

Sant
Click to expand...


My first question is where does your reset (r) come from? If it comes
from an external pin then it will be difficult to design something that
works if reset pulses and is gone before the first clock edge or starts
out active so that you never see a rising edge.

But if you do that then your circuit can't work because the reset is not
synchronized to the clock and you will not meet setup/hold time. You
have to have a filter on the reset to meet timing. Make sure the filter
has at least two stages to sync reset to the clock.


If you filter your reset signal then your design becomes easy.



module DFFR(d,clk,r, q) ;
input d, clk,r ;
output wire q ;

reg q_p;

always @(posedge clk )
if (r) q_p <= 0 ;
else q_p <= d ;

assign q = q_p & r;

endmodule



But even this is overkill. If your q output goes to another flop that
also has a sync reset then the only time that you gate the q output is
during reset when the output is never used because the receiving flop is
being reset.

You can leave out all the output gating unless the signal is an output
that leaves the chip. You can gate all those signals in a wrapper and
never touch your core rtl logic.






John Eaton
 
John Eaton wrote:
santhosh_h_98@yahoo.com wrote:
Hi,

I know DFF is:

module DFF(d,clk,q) ;
input d, clk ;
output reg q ;

always @(posedge clk)
q<= d ;
endmodule

Now I need to implement ASYNCHRONOUS RESET flip flop
using DFF ONLY, may be some extract logic. HOW CAN I DO THAT ?

The implemented circuit MUST WORK AS FOLLOWS:

module DFFR(d,clk,r, q) ;
input d, clk,r ;
output reg q ;

always @(posedge clk or posedge r)
if (r) q <= 0 ;
else q<= d ;
endmodule

Please give the code or diagram. I am curious about this.

Sant



My first question is where does your reset (r) come from? If it comes
from an external pin then it will be difficult to design something that
works if reset pulses and is gone before the first clock edge or starts
out active so that you never see a rising edge.

But if you do that then your circuit can't work because the reset is not
synchronized to the clock and you will not meet setup/hold time. You
have to have a filter on the reset to meet timing. Make sure the filter
has at least two stages to sync reset to the clock.


If you filter your reset signal then your design becomes easy.



module DFFR(d,clk,r, q) ;
input d, clk,r ;
output wire q ;

reg q_p;

always @(posedge clk )
if (r) q_p <= 0 ;
else q_p <= d ;

assign q = q_p & r;

endmodule



But even this is overkill. If your q output goes to another flop that
also has a sync reset then the only time that you gate the q output is
during reset when the output is never used because the receiving flop is
being reset.

You can leave out all the output gating unless the signal is an output
that leaves the chip. You can gate all those signals in a wrapper and
never touch your core rtl logic.






John Eaton






Missed an inversion. I'm used to always using active low async resets.
Click to expand...


module DFFR(d,clk,r, q) ;
input d, clk,r ;
output wire q ;

reg q_p;

always @(posedge clk )
if (r) q_p <= 0 ;
else q_p <= d ;

assign q = q_p & (~r);

endmodule
 
On Jan 5, 10:28 am, John Eaton <no_s...@spam.com> wrote:
John Eaton wrote:
santhosh_h...@yahoo.com wrote:
Hi,

I know DFF is:

module DFF(d,clk,q) ;
     input d, clk ;
     output reg q ;

     always @(posedge clk)
           q<= d ;
endmodule

Now I need to implement ASYNCHRONOUS RESET flip flop
using DFF ONLY, may be some extract logic. HOW CAN I DO THAT ?

The implemented circuit MUST WORK AS FOLLOWS:

module DFFR(d,clk,r, q) ;
     input d, clk,r ;
     output reg q ;

     always @(posedge clk or posedge r)
          if (r) q <= 0 ;
          else  q<= d ;
endmodule

Please give the code or diagram. I am curious about this.

Sant

My first question is where does your reset (r) come from? If it comes
from an external pin then it will be difficult to design something that
works if reset pulses and is gone before the first clock edge or starts
out active so that you never see a rising edge.

But if you do that then your circuit can't work because the reset is not
synchronized to the clock and you will not meet setup/hold time. You
have to have a filter on the reset to meet timing. Make sure the filter
has at least two stages to sync reset to the clock.

If you filter your reset signal then your design becomes easy.

module DFFR(d,clk,r, q) ;
      input d, clk,r ;
      output wire q ;

      reg q_p;

      always @(posedge clk )
           if (r) q_p <= 0 ;
           else   q_p <= d ;

     assign q = q_p & r;

 endmodule

But even this is overkill. If your q output goes to another flop that
also has a sync reset then the only time that you gate the q output is
during reset when the output is never used because the receiving flop is
being reset.

You can leave out all the output gating unless the signal is an output
that leaves the chip. You can gate all those signals in a wrapper and
never touch your core rtl logic.

John Eaton

Missed an inversion. I'm used to always using active low async resets.

module DFFR(d,clk,r, q) ;
        input d, clk,r ;
        output wire q ;

        reg q_p;

        always @(posedge clk )
             if (r) q_p <= 0 ;
             else   q_p <= d ;

       assign q = q_p & (~r);

   endmodule
Click to expand...
I don't see how this logic would work properly. Assume q_p is a 1,
then pulse
the reset signal for a very short time.

In a real DFFR, the flop would clear and stay cleared.
In this code, the output will pulse low then go back to a high
state (assuming the clock has not wiggled while reset is asserted).

John Providenza
 
jprovidenza@yahoo.com wrote:
On Jan 5, 10:28 am, John Eaton <no_s...@spam.com> wrote:
John Eaton wrote:
santhosh_h...@yahoo.com wrote:
Hi,
I know DFF is:
module DFF(d,clk,q) ;
input d, clk ;
output reg q ;
always @(posedge clk)
q<= d ;
endmodule
Now I need to implement ASYNCHRONOUS RESET flip flop
using DFF ONLY, may be some extract logic. HOW CAN I DO THAT ?
The implemented circuit MUST WORK AS FOLLOWS:
module DFFR(d,clk,r, q) ;
input d, clk,r ;
output reg q ;
always @(posedge clk or posedge r)
if (r) q <= 0 ;
else q<= d ;
endmodule
Please give the code or diagram. I am curious about this.
Sant
My first question is where does your reset (r) come from? If it comes
from an external pin then it will be difficult to design something that
works if reset pulses and is gone before the first clock edge or starts
out active so that you never see a rising edge.
But if you do that then your circuit can't work because the reset is not
synchronized to the clock and you will not meet setup/hold time. You
have to have a filter on the reset to meet timing. Make sure the filter
has at least two stages to sync reset to the clock.
If you filter your reset signal then your design becomes easy.
module DFFR(d,clk,r, q) ;
input d, clk,r ;
output wire q ;
reg q_p;
always @(posedge clk )
if (r) q_p <= 0 ;
else q_p <= d ;
assign q = q_p & r;
endmodule
But even this is overkill. If your q output goes to another flop that
also has a sync reset then the only time that you gate the q output is
during reset when the output is never used because the receiving flop is
being reset.
You can leave out all the output gating unless the signal is an output
that leaves the chip. You can gate all those signals in a wrapper and
never touch your core rtl logic.
John Eaton
Missed an inversion. I'm used to always using active low async resets.

module DFFR(d,clk,r, q) ;
input d, clk,r ;
output wire q ;

reg q_p;

always @(posedge clk )
if (r) q_p <= 0 ;
else q_p <= d ;

assign q = q_p & (~r);

endmodule

I don't see how this logic would work properly. Assume q_p is a 1,
then pulse
the reset signal for a very short time.

In a real DFFR, the flop would clear and stay cleared.
In this code, the output will pulse low then go back to a high
state (assuming the clock has not wiggled while reset is asserted).

John Providenza
Click to expand...

Thats why you must filter your reset. The external reset could be a very
short pulse but the filter will sync it to clk and stretch it to at
least two clock periods. The first clock will reset the flop.


John Eaton
 
On Dec 23 2008, 7:57 am, santhosh_h...@yahoo.com wrote:
Hi,

I know DFF is:

module DFF(d,clk,q) ;
     input d, clk ;
     output reg q ;

     always @(posedge clk)
           q<= d ;
endmodule

Now I need to implement ASYNCHRONOUS RESET flip flop
using DFF ONLY, may be some extract logic. HOW CAN I DO THAT ?

The implemented circuit MUST WORK AS FOLLOWS:

module DFFR(d,clk,r, q) ;
     input d, clk,r ;
     output reg q ;

     always @(posedge clk or posedge r)
          if (r) q <= 0 ;
          else  q<= d ;
endmodule

Please give the code or diagram. I am curious about this.

Sant
Click to expand...
Well, it seems that we lost the OP a long time ago, but this
sparked my curiosity, so I gave it some more thought and it
seems to me that unless you want to create edge-triggered
circuits from gates, the only way to accomplish this is
to use more than one DFF (in addition to some gates). One
possible solution is:

module DFFR(
input D,
input CLK,
input R,
output Q
);

wire q_int, rst_int, rst_hold, rst_clr;

DFF main_dff (.d (D), .clk (CLK), .q (q_int));

DFF rst_dff (.d (rst_int & !R), .clk (CLK), .q (rst_clr));

assign rst_int = R | rst_hold;
assign rst_hold = rst_int & !rst_clr;

assign Q = q_int & !rst_int;

endmodule

The second DFF creates the clear function for rst_int
which holds the internal reset signal until the next
rising edge of the clock.

This will have some issues in simulation if your
DFF primitive does not have an initial value. You
can work around this my asserting R long enough to
encompass one rising egde of CLK.

Regards,
Gabor
 
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