Device 0 Unit 0:waiting for core to be armed, slow or stoppe

[jypa09]

Hello

I'm Implementing controller using xilinx ISE 8.2 on FPGA board Virtex-I
and anlyzing signals inside FPGA using chiscope analyzer.

I instantiated cores using chipscope core inserter.My implementation wa
successful.

Though the bit file was generated but when it comes to analyze it i
chipscope ,,,I could get this problem

Device 0 Unit 0:waiting for core to be armed, slow or stopped clock..
When I implemented the design..I could get the only warning ..i,e
WARNING:Timing:3223 - Timing constraint PATH "TS_U_TO_D_path" TIG; ignore
during timing analysis.

and the rest like generating programming file everything is going well
but when it come sto analyze it in chipscope after configuring it with bi
file...I could get the error like

Device 0 Unit 0:waiting for core to be armed, slow or stopped clock..

I have tried to manage it by reading so many forums...like nearly I change
all possible changes but still I could get this...
Its a big design so I assigned pin only for clock signal with help o
manual..
and the signal I selected for a clock to Chipscope is driven by
a BUFG or BUFGMUX component...
mhz_in signal is not being driven by the board.
clock source (on-board) was driven by the pin I assigned
to it in .ucf file...but still I could get this problem..

Can anybody help me ...Please..






---------------------------------------
Posted through http://www.FPGARelated.com

 

[d_s_klein]

On Nov 10, 6:37 am, "jypa09" <jyothirmai.aksha@n_o_s_p_a_m.gmail.com>
wrote:

Hello

I'm Implementing controller using xilinx ISE 8.2  on FPGA board Virtex-II
and anlyzing signals inside FPGA using chiscope analyzer.

I instantiated cores using chipscope core inserter.My implementation was
successful.

Though the bit file was generated  but when it comes to analyze it in
chipscope ,,,I could get this problem

Device 0 Unit 0:waiting for core to be armed, slow or stopped clock..
When I implemented the design..I could get the only warning ..i,e
WARNING:Timing:3223 - Timing constraint PATH "TS_U_TO_D_path" TIG; ignored
during timing analysis.

and the rest like generating programming file everything is going well
but when it come sto analyze it in chipscope after configuring it with bit
file...I could get the error like

Device 0 Unit 0:waiting for core to be armed, slow or stopped clock..

I have tried to manage it by reading so many forums...like nearly I changed
all possible changes but still I could get this...
Its a big design so I assigned pin only  for clock signal with help of
manual..
and the signal I selected for a clock to Chipscope is driven by
a BUFG or BUFGMUX component...
mhz_in signal is not being driven by the board.
clock source (on-board) was driven by the pin I assigned
to it in .ucf file...but still I could get this problem..

Can anybody help me ...Please..

---------------------------------------        
Posted throughhttp://www.FPGARelated.com

You have two different messages telling you that the clock is not
connected to the ILA.

#1: "slow or stopped clock" - This message indicates that the
Chipscope application timed out waiting for the ILA to report ready -
all it needs is a clock for it to respond.

#2: "timing path ignored" - In this case it's trying to tell you that
it didn't find a clock on the specified path.

I realize that you think you have connected a clock. However, ISE is
not convinced.

RK