develop a state diagram for the DTE VHDL code

[vick]

hi to all:
i have problem of drawing the state diagram could anyone please help
me out thank alot


library IEEE;
USE ieee.std_logic_1164.ALL;

ENTITY dte IS PORT ( rst,dcr,ri,cd,cts,rxd,data,clk: in std_logic;
dtr,start,rts,txd,out_dte: out std_logic);
END dte;

ARCHITECTURE dte_arch OF dte IS
TYPE state IS (st0,st1,st2,st3,st4,st5,st6,st7,st8,st9,
st10,st11,st12,st13,st14,st15,st16,st17,st18,st19,
st20,st21,st22,st23,st24,st25,st26,st27,st28,st29);

SIGNAL present_dte,next_dte:STATE;

BEGIN

processdte: PROCESS (rst,dcr,ri,cd,cts,rxd,data,clk)
BEGIN
if rst='0' then
present_dte<=st0;
elsif (clk'event and clk='1') then
present_dte<=next_dte;
end if;

dtr <= '1';
start <= '0';
rts <= '0';
txd <= '0';
out_dte <= '0';

CASE present_dte IS

WHEN st0 => dtr <= '1';start <= '0';rts <= '0'; txd <= '0'; out_dte
<= '0';
IF data = '1' THEN
next_dte <= st1;
ELSIF ri = '1' THEN
next_dte <= st15;
ELSE
next_dte <= st0;
END IF;

WHEN st1 => dtr <= '1';start <= '1';rts <= '0'; txd <= '0'; out_dte
<= '0';
IF cd = '0' THEN
next_dte <= st1;
ELSE
next_dte <= st2;
END IF;

WHEN st2 => dtr <= '1';start <= '0';rts <= '0'; txd <= '0'; out_dte
<= '0';
IF rxd= '0' THEN
next_dte <= st2;
ELSE
next_dte <= st3;
END IF;

WHEN st3 => dtr <= '1';start <= '0';rts <= '0'; txd <= '0'; out_dte
<= '0';
IF rxd = '0' THEN
next_dte <= st0;
ELSE
next_dte <= st4;
END IF;

WHEN st4 => dtr <= '1';start <= '0';rts <= '0'; txd <= '0'; out_dte
<= '0';
IF cd = '1' THEN
next_dte <= st4;
ELSE
next_dte <= st5;
END IF;

WHEN st5 => dtr <= '1';start <= '0';rts <= '1'; txd <= '0'; out_dte
<= '0';
IF cts = '0' THEN
next_dte <= st5;
ELSE
next_dte <= st6;
END IF;

WHEN st6 => dtr <= '1';start <= '0';rts <= '1'; txd <= '0'; out_dte
<= '1';
next_dte <= st7;

WHEN st7 => dtr <= '1';start <= '0';rts <= '1'; txd <= '0'; out_dte
<= '0';
IF data = '0' THEN
next_dte <= st7;
ELSE
next_dte <= st8;
END IF;

WHEN st8 => dtr <= '1';start <= '0';rts <= '1'; txd <= '1'; out_dte
<= '0';
IF data = '0' THEN
next_dte <= st9;
ELSE
next_dte <= st11;
END IF;

WHEN st9 => dtr <= '1';start <= '0';rts <= '1'; txd <= '0'; out_dte
<= '0';
IF data = '0' THEN
next_dte <= st10;
ELSE
next_dte <= st12;
END IF;

WHEN st10 => dtr <= '1';start <= '0';rts <= '1'; txd <= '0'; out_dte
<= '1';
next_dte <= st13;

WHEN st11 => dtr <= '1';start <= '0';rts <= '1'; txd <= '1'; out_dte
<= '0';
IF data = '0' THEN
next_dte <= st10;
ELSE
next_dte <= st12;
END IF;

WHEN st12 => dtr <= '1';start <= '0';rts <= '1'; txd <= '1'; out_dte
<= '1';
next_dte <= st13;

WHEN st13 => dtr <= '1';start <= '0';rts <= '1'; txd <= '1'; out_dte
<= '0';
IF data = '1' THEN
next_dte <= st8;
ELSE
next_dte <= st14;
END IF;

WHEN st14 => dtr <= '1';start <= '0';rts <= '0'; txd <= '0'; out_dte
<= '0';
IF cts = '1' THEN
next_dte <= st14;
ELSE
next_dte <= st0;
END IF;

WHEN st15 => dtr <= '1';start <= '0';rts <= '1'; txd <= '0'; out_dte
<= '0';
IF cts = '0' THEN
next_dte <= st15;
ELSE
next_dte <= st16;
END IF;

WHEN st16 => dtr <= '1';start <= '0';rts <= '1'; txd <= '1'; out_dte
<= '0';
IF data = '0' THEN
next_dte <= st19;
ELSE
next_dte <= st17;
END IF;

WHEN st17 => dtr <= '1';start <= '0';rts <= '1'; txd <= '0'; out_dte
<= '0';
next_dte <= st18;

WHEN st18 => dtr <= '1';start <= '0';rts <= '1'; txd <= '0'; out_dte
<= '0';
next_dte <= st29;

WHEN st19 => dtr <= '1';start <= '0';rts <= '1'; txd <= '1'; out_dte
<= '0';
next_dte <= st20;

WHEN st20 => dtr <= '1';start <= '0';rts <= '1'; txd <= '1'; out_dte
<= '0';
next_dte <= st21;

WHEN st21 => dtr <= '1';start <= '0';rts <= '1'; txd <= '1'; out_dte
<= '0';
next_dte <= st22;

WHEN st22 => dtr <= '1';start <= '0';rts <= '0'; txd <= '0'; out_dte
<= '0';
IF (cd = '1' AND rxd = '1') THEN
next_dte <= st23;
ELSE
next_dte <= st22;
END IF;

WHEN st23 => dtr <= '1';start <= '0';rts <= '0'; txd <= '0'; out_dte
<= '1';
IF rxd = '0' THEN
next_dte <= st24;
ELSE
next_dte <= st26;
END IF;

WHEN st24 => dtr <= '1';start <= '0';rts <= '0'; txd <= '0'; out_dte
<= '0';
IF rxd = '0' THEN
next_dte <= st25;
ELSE
next_dte <= st27;
END IF;

WHEN st25 => dtr <= '1';start <= '0';rts <= '0'; txd <= '0'; out_dte
<= '0';
next_dte <= st28;

WHEN st26 => dtr <= '1';start <= '0';rts <= '0'; txd <= '0'; out_dte
<= '1';
IF rxd = '1' THEN
next_dte <= st27;
ELSE
next_dte <= st25;
END IF;

WHEN st27 => dtr <= '1';start <= '0';rts <= '0'; txd <= '0'; out_dte
<= '1';
next_dte <= st28;

WHEN st28 => dtr <= '1';start <= '0';rts <= '0'; txd <= '0'; out_dte
<= '1';
IF rxd = '1' THEN
next_dte <= st23;
ELSE
next_dte <= st0;
END IF;

WHEN st29 => dtr <= '1';start <= '0';rts <= '1'; txd <= '1'; out_dte
<= '0';
next_dte <= st0;

END CASE;

END PROCESS;

END dte_arch;