Determining width of a variable?

E

Evan Lavelle

Guest
Is it possible to define an expression which evaluates to the defined
width of an arbitrary variable?

There's a $clog2 defined in V-2005, but it doesn't seem to be widely
supported. It's easy to write your own clog2 which returns the width
of a variable. However, this doesn't give you the right answer - it
only tells you the index of the top set bit at the time that it's
called.

To get the defined width of a variable, you need to set it to all 1's,
or at least set the top bit; an expression like 'var - var - 1'b1'
will do this for you. So, the question now is - how do you find the
number of set bits in this, or a similar, expression?

If you do a clog2-look-alike, you're likely to end up with something
like

((var - var - 1'b1) >= (1 << 16))? ... : ... // etc

This is where it falls over - the size of the literal '1' gets
propagated back to 'var' before the left-hand expression is evaluated,
and the LH expression ends up as 32'hffffffff, which is useless. I've
spent a couple of hours looking at this and the expression sizing
rules seem to screw up any attempt to do this. The obvious fix of
assigning (var - var - 1'b1) to a temporary doesn't work either, since
you have to know the size of var to get the size of the temporary,
which defeats the purpose of the exercise.

Any thoughts?

Thanks -

Evan
 
Evan Lavelle wrote:
Is it possible to define an expression which evaluates to the defined
width of an arbitrary variable?
Any thoughts?
Does this work for you?

function integer log2 ;
input [31:0] arg ;
for (log2=0; arg > 0; log2=log2+1)
arg = arg >> 1 ;
endfunction // log2


-- Mike Treseler
 
Evan Lavelle wrote:
If you do a clog2-look-alike, you're likely to end up with something
like

((var - var - 1'b1) >= (1 << 16))? ... : ... // etc

This is where it falls over - the size of the literal '1' gets
propagated back to 'var' before the left-hand expression is evaluated,
and the LH expression ends up as 32'hffffffff, which is useless. I've
spent a couple of hours looking at this and the expression sizing
rules seem to screw up any attempt to do this.
You can isolate a subexpression from the context-determined sizing by
putting it inside a one-element concatenation, whose operands are self-
determined.

({var - var - 1'b1} >= (1<<16))? ...

You could similarly use $signed or $unsigned, since their arguments
are also self-determined. You might want to use $unsigned anyway, so
you know your compares are unsigned.

(($unsigned(var - var - 1'b1) >= (1<<16))?
 
On Wed, 12 Sep 2007 14:05:38 -0700, Mike Treseler
<mike_treseler@comcast.net> wrote:

Evan Lavelle wrote:
Is it possible to define an expression which evaluates to the defined
width of an arbitrary variable?
Any thoughts?

Does this work for you?

function integer log2 ;
input [31:0] arg ;
for (log2=0; arg > 0; log2=log2+1)
arg = arg >> 1 ;
endfunction // log2
Afraid not. An expression such as "width = log2(t1 - t1 - 1'b1)"
doesn't get around the sizing problem; you're effectively assigning
"t1 - t1 - 1'b1" to "arg", which expands t1. The issue isn't the
derivation of the log (you can write a single conditional operator
expression which derives the log in 5 comparisons), but how you go
about defeating the expression sizing rules, which just get in the way
here.

Evan
 
Mike Treseler wrote:
Does this work for you?

function integer log2 ;
input [31:0] arg ;
for (log2=0; arg > 0; log2=log2+1)
arg = arg >> 1 ;
endfunction // log
The problem with this is the same as with the temporary variable (in
fact, arg acts as that temporary variable). When the (var-var-1'b1)
gets evaluated and passed to arg, it will get evaluated at a minimum
of the width of arg, or 32 bits, and then truncated to the width of
arg. So the answer will always come back as if the width were 32.
 
On Wed, 12 Sep 2007 14:44:09 -0700, sharp@cadence.com wrote:


You can isolate a subexpression from the context-determined sizing by
putting it inside a one-element concatenation, whose operands are self-
determined.

({var - var - 1'b1} >= (1<<16))? ...
Excellent - that did it. I'd rather stick to V-95, so I prefer this to
$unsigned.

Thanks -

Evan
 
Evan Lavelle wrote:

but how you go
about defeating the expression sizing rules, which just get in the way
here.
I don't know if this is apropos, but when I
convert vhdl to verilog for synthesis, I assign a parameter
value to a reg array to emulate a vhdl constant vector.

See "zero_big_c" here, for example.

http://home.comcast.net/~mike_treseler/count_enable.v

-- Mike Treseler
 
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Evan Lavelle wrote:
Is it possible to define an expression which evaluates to the defined
width of an arbitrary variable?
Uh, does $bits(<expr>) do it for you? (Probably not portable, but
if your <expr> is a variable, you can always implemented it it PLI
for those places where it doesn't exist natively.


- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
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On Wed, 12 Sep 2007 20:50:14 -0700, Stephen Williams
<spamtrap@icarus.com> wrote:

Uh, does $bits(<expr>) do it for you? (Probably not portable, but
if your <expr> is a variable, you can always implemented it it PLI
for those places where it doesn't exist natively.
It would, but it's not Verilog :) I tried it in Icarus, though, and
it does the job.

[Wasn't the IEEE committee going to decide whether or not SV was
Verilog? What happened?]
 
On Thu, 13 Sep 2007 09:15:50 +0100,
Evan Lavelle <nospam@nospam.com> wrote:

[Wasn't the IEEE committee going to decide
whether or not SV was Verilog? What happened?]
It's in progress. The plan is that IEEE 1800-2008 will be
SystemVerilog and will have the whole of 1364 as a subset.
A draft merged LRM already exists and is currently under
review; as you might imagine, many tweaks and clarifications
to SystemVerilog are taking place as part of the same effort.
Some of the tweaks, particularly with regard to the assertions
language, are on a chainsaw-and-JCB[*] scale, but
that's merely a detail...

Ballotting should be some time in the spring - I don't have
the exact dates to hand.

[*] for non-Brit readers, JCB is the best-known British make
of backhoes and earthmovers.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
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