Determing change in signals....

[Nimesh Shahdadpuri]

I wish to monitor two signals in verilog and then determine which of the changed first and then do some work accordingly. I have two signals, sel1 and sel2, which i need to monitor.

Verilog code :

module tb(
input sel1,
input sel2
);

//Determine which of the two changed first

//if sel1 changed first :
//Do some work
//else
//Do some other work.

Please help
thank you

 

[Rick C]

On Sunday, June 14, 2020 at 3:09:32 PM UTC-4, Nimesh Shahdadpuri wrote:

I wish to monitor two signals in verilog and then determine which of the changed first and then do some work accordingly. I have two signals, sel1 and sel2, which i need to monitor.

Verilog code :

module tb(
input sel1,
input sel2
);

//Determine which of the two changed first

//if sel1 changed first :
//Do some work
//else
//Do some other work.

Please help
thank you

Is this code only for simulation or do you need to construct hardware?

That\'s the first question that has to be answered.

--

Rick C.

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