K
Kenneth Brun Nielsen
Guest
I've created a Verilog model of a DUT and a testbench in order to
effectively generate test vectors through the Icarus simulator. The
target is to use the test vectors on the silicon device.
Any ideas to how I can achieve a measure of test coverage? I've been
looking at Covered (http://covered.sourceforge.net/user/index.html),
and it seems to perform a measurement of how many nodes was toggled
from 0 to 1 and vice versa. As I see it, this is not sufficient. It is
not enough to ensure, that a given node was toggled - we also have to
make sure, that if the node is NOT toggled in the silicon device (e.g.
due to some 'stuck at' error) we should be able to see it at the chip
outputs.
Any ideas how to perform this measurement? Any tools? Free-ware?
Best regards,
Kenneth
effectively generate test vectors through the Icarus simulator. The
target is to use the test vectors on the silicon device.
Any ideas to how I can achieve a measure of test coverage? I've been
looking at Covered (http://covered.sourceforge.net/user/index.html),
and it seems to perform a measurement of how many nodes was toggled
from 0 to 1 and vice versa. As I see it, this is not sufficient. It is
not enough to ensure, that a given node was toggled - we also have to
make sure, that if the node is NOT toggled in the silicon device (e.g.
due to some 'stuck at' error) we should be able to see it at the chip
outputs.
Any ideas how to perform this measurement? Any tools? Free-ware?
Best regards,
Kenneth