detecting x values in simulation globally

[Jürgen Böhm]

Hi,

currently I am doing some hobby projects with an FPGA and use Verilog
as HDL together with Icarus as a simulator.
Now it would be very helpful (at least I think so) to detect any case
of occurring "x" values on any signal that is part of the design under
test. Of course one could write exhaustive $monitor statements by hand
and use grep on the text-output, but this seems to be quite tedious a
procedure. Are there a simpler ways to achieve this result?

Thanks in advance for any answers!

Jürgen

--
Jürgen Böhm www.aviduratas.de
"At a time when so many scholars in the world are calculating, is it not
desirable that some, who can, dream ?" R. Thom

 

[Yottameter]

PLI is a way to go. The book "Verilog PLI Handbook" by Sutherland has an
example in it that is pretty close to what you want. Just pass in the
top level scope, and the PLI will iterate through the heirarchy.



Jürgen Böhm wrote:

Hi,

currently I am doing some hobby projects with an FPGA and use Verilog
as HDL together with Icarus as a simulator.
Now it would be very helpful (at least I think so) to detect any case
of occurring "x" values on any signal that is part of the design under
test. Of course one could write exhaustive $monitor statements by hand
and use grep on the text-output, but this seems to be quite tedious a
procedure. Are there a simpler ways to achieve this result?

Thanks in advance for any answers!

Jürgen