detecting if instance is toplevel

[Peter Riocreux]

I have some modules that, if a particular symbol is `defined will
report their use and parameter values. However the top level module
definition also does this (at least) if it is not used in several
(all?) simulators. I would like to suppress this, but cannot think of
any mechanism to determine/check what the scope of an instance is. I
am loathe to write a $display replacement VPI just to get around this.

Any suggestions?

Regards,

Peter

 

[Steven Sharp]

Peter Riocreux <par+usenet@silistix.com> wrote in message news:<85hdxdel0g.fsf@fathom.silistix.com>...

I would like to suppress this, but cannot think of
any mechanism to determine/check what the scope of an instance is.

It is possible in Verilog-2001, though it would be a kludge. You
could use the %m format descriptor (which prints the full hierarchical
name of the scope where it appears), with the new $swrite system task
(which writes a string into a reg, rather than to the output). Then
you could have the code examine the reg value. If you aren't worried
about escaped names, you could just check for "." characters in it
to see if the name is a top-level scope.