Detecting cold reset on flash FPGA

J

JB

Guest
Hello,

I'm working on a project involving an actel flash FPGA (A3P250) and I
need to discriminate cold resets (reset at power up) from warm resets.

As the power up level of my registers is unknown, I can't find any
good way of doing this.
The best solution I came up with so far is the following:
- Use an n-Bit wide register
- When the FPGA is reset compare the register with a "magic value" A,
if it is equal to A then it is a warm reset
- When the FPGA is reset load the register with A

This will work most of the time but has one chance over 2^n to detect
a warm reset at power up (if the register powers-up containing A).

Is there any best way of detecting a cold boot?

Thanks is advance.
JB Dubois
 
"JB" <jb.dubois.jbd@gmail.com> wrote in message
news:32d6bdbb-8616-4a6f-946a-22cc2aa09d96@m11g2000vbs.googlegroups.com...
Hello,

I'm working on a project involving an actel flash FPGA (A3P250) and I
need to discriminate cold resets (reset at power up) from warm resets.

Is there any best way of detecting a cold boot?
Click to expand...
I would assume you could just put an attribute to a FF telling it should be
high or low at init, and write code to change its state when read.
 
"Morten Leikvoll" <mleikvol@yahoo.nospam> wrote in message
news:DPednbEEsKCGvbrQnZ2dnUVZ8sidnZ2d@lyse.net...
"JB" <jb.dubois.jbd@gmail.com> wrote in message
news:32d6bdbb-8616-4a6f-946a-22cc2aa09d96@m11g2000vbs.googlegroups.com...
Hello,

I'm working on a project involving an actel flash FPGA (A3P250) and I
need to discriminate cold resets (reset at power up) from warm resets.

Is there any best way of detecting a cold boot?

I would assume you could just put an attribute to a FF telling it should
be high or low at init, and write code to change its state when read.
Click to expand...
You could TRY this, but I guess its a bit dependant on the synth tool if it
actually uses the init value of the signal.

signal hotboot:STD_LOGIC:='1';
...
if(rising_edge(clk)) then
if(warmreset='1') then -- for syncronous warm reset
hotboot<='0';
end if;
end if;
..
..
 
Sorry for not thinking flash. I guess you need some external powerup signal
(poweron reset) to set a FF then. And the warm reset needs to be separate
from this.

"JB" <jb.dubois.jbd@gmail.com> wrote in message
news:86367b28-3d01-48f0-beb0-33e53bf49dd9@l22g2000vbp.googlegroups.com...
On 7 jan, 15:22, "Morten Leikvoll" <mleik...@yahoo.nospam> wrote:
"Morten Leikvoll" <mleik...@yahoo.nospam> wrote in message

You could TRY this, but I guess its a bit dependant on the synth tool if
it
actually uses the init value of the signal.

signal hotboot:STD_LOGIC:='1';
..
if(rising_edge(clk)) then
if(warmreset='1') then -- for syncronous warm reset
hotboot<='0';
end if;
end if;
.
Click to expand...
It will work on SRAM FPGA but as far as I know flash FPGA can't use
initial values for their FF.

At least it is not specified by Actel, and as the project targets a
secure aeronautical function, I can't justify the design just by
saying "I tried it a few times, it seems to be working..."

Do one of you know anything about FF power up level on flash (or
antifuse) FPGA which may not be specified by actel but still true?
 
On 7 jan, 15:22, "Morten Leikvoll" <mleik...@yahoo.nospam> wrote:
"Morten Leikvoll" <mleik...@yahoo.nospam> wrote in message

You could TRY this, but I guess its a bit dependant on the synth tool if it
actually uses the init value of the signal.

signal hotboot:STD_LOGIC:='1';
..
if(rising_edge(clk)) then
    if(warmreset='1') then -- for syncronous warm reset
        hotboot<='0';
    end if;
end if;
.
Click to expand...
It will work on SRAM FPGA but as far as I know flash FPGA can't use
initial values for their FF.

At least it is not specified by Actel, and as the project targets a
secure aeronautical function, I can't justify the design just by
saying "I tried it a few times, it seems to be working..."

Do one of you know anything about FF power up level on flash (or
antifuse) FPGA which may not be specified by actel but still true?
 
On 1/7/2011 7:07 AM, Morten Leikvoll wrote:
Sorry for not thinking flash. I guess you need some external powerup signal
(poweron reset) to set a FF then. And the warm reset needs to be separate
from this.

"JB"<jb.dubois.jbd@gmail.com> wrote in message
news:86367b28-3d01-48f0-beb0-33e53bf49dd9@l22g2000vbp.googlegroups.com...
On 7 jan, 15:22, "Morten Leikvoll"<mleik...@yahoo.nospam> wrote:
"Morten Leikvoll"<mleik...@yahoo.nospam> wrote in message

You could TRY this, but I guess its a bit dependant on the synth tool if
it
actually uses the init value of the signal.

signal hotboot:STD_LOGIC:='1';
..
if(rising_edge(clk)) then
if(warmreset='1') then -- for syncronous warm reset
hotboot<='0';
end if;
end if;
.

It will work on SRAM FPGA but as far as I know flash FPGA can't use
initial values for their FF.

At least it is not specified by Actel, and as the project targets a
secure aeronautical function, I can't justify the design just by
saying "I tried it a few times, it seems to be working..."

Do one of you know anything about FF power up level on flash (or
antifuse) FPGA which may not be specified by actel but still true?
Click to expand...
Hang a ceramic cap off an IO pin. Use it as a 1 bit memory.

--
Rob Gaddi, Highland Technology
Email address is currently out of order
 
Hang a ceramic cap off an IO pin.  Use it as a 1 bit memory.

--
Rob Gaddi, Highland Technology
Email address is currently out of order
Click to expand...

How will you be sure that the capacitor will not be loaded by the FPGA
on cold reset? By not putting any FF in the path (assuming that is it
logically valid)?
 
On Jan 8, 3:48 am, JB <jb.dubois....@gmail.com> wrote:
At least it is not specified by Actel, and as the project targets a
secure aeronautical function, I can't justify the design just by
saying "I tried it a few times, it seems to be working..."

Do one of you know anything about FF power up level on flash (or
antifuse) FPGA which may not be specified by actel but still true?
Click to expand...
I'd step back a little, as even if the silicon does have a
rudimentary POR, those do NOT correctly register a brown out event.

So you need a proper Vcc driven reset device, and that can easily set
a 'Hard POR' signature, FF, which is later changed by SW to a Soft-
boot state.
- especially in a 'secure aeronautical function', you should be
avoiding any possible brownout operation.

-jg
 
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