Detailed Specification of IEEE802.11 MAC for Synthesis

[server]

message unavailable

 

[Charles Edmondson]

Parth wrote:

Hi, I am trying to implement IEEE 802.11 wireless MAC transmitter on
SYNOPSYS. I have the standard but apart from that I haven't found any
kind of specifications.
Can anybody guide me where I can get detailed block diagram and
specifications for 802.11/802.11b

It will be of great help.

Sincerely,
Parth Malani.

What toolset? Since you said Synopsys, you must be doing an ASIC or
similiar chip, otherwise I would have asked what chipset you were
building with. Sounds like you need to be looking at IP vendors...
--
Charlie
--
Edmondson Engineering
Unique Solutions to Unusual Problems

 

[neil]

well this is an interesting coded message not unlike one that appeared post
911 talking about stadiums and monuments...hmmm....did anyone report that
one at the time?

 

[me]

<Victim_of_American_Stupidity@bixkykur.edu.ua> wrote in message
news:B2B8AE742B11326D4EF6F7040D@NEWS.GRADWELL.NET...

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Now that makes more sense.

 

[What-a-Tool]

Actually, if you poke around in other news groups, over time you will see a
lot of these strange looking gibberish messages. A lot of them even seem to
have Arabic sounding references in them.
They probably are just that - gibberish posted by brain damaged individuals,
like this guy with the posts about the FBI tracking him with a transponder
chip, the one who is obsessed with aluminum foil.

On the extremely off chance that it was something more, I did however send a
note to the FBI from their Tips and Information web site. Never heard
anything about it again.

--

/ Sean the Mc /

"Opinions are like flatulence - everyone loves the sound of their own, but
anyone else's usually just stinks !"
-anonymous


"neil" <neilscad@hotmail.com> wrote in message
news:HHEjd.5065$op3.191279@news.xtra.co.nz...

well this is an interesting coded message not unlike one that appeared
post 911 talking about stadiums and monuments...hmmm....did anyone report
that one at the time?

 

[Cliff]

On Fri, 31 Dec 2004 02:06:49 GMT, dekeytaylor@hotmail.com wrote:

<snip>

Looks like, after many redirections, it leads to a Javascript
intended to hijack your browser and who knows how much
else?
--
Cliff

 

[Ariane]

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--
Posted by News Bulk Poster
Unregistered version

 

[Randy Howard]

In article <2df53916.0504270544.5555e8bc@posting.google.com>, amosw01
@yahoo.com.tw says...

Ąˇ¸ó°ęąĐ¨|ĄAŠMĽ@ŹÉľ×­^¤ń¸ŁłU

42.

--
Randy Howard (2reply remove FOOBAR)
"Making it hard to do stupid things often makes it hard
to do smart ones too." -- Andrew Koenig

 

[Tux Wonder-Dog]

I agree, it would be a mercy killing.

Rick Osborn wrote:

dang, what an annoying little bug. somebody slap him.

--
"Good, late in to more rewarding well."  "Well, you tonight.  And I was
lookintelligent woman of Ming home.  I trust you with a tender silence."  I
get a word into my hands, a different and unbelike, probably - 'she
fortunate fat woman', wrong word.  I think to me, I justupid.
Let not emacs meta-X dissociate-press write your romantic dialogs...!!!

 

[Alvin Andries]

"cricketlover" <dpgulati@cs.utexas.edu> wrote in message
news:1117663768.902404.31350@g14g2000cwa.googlegroups.com...

I am not sure if this is the right place to put this question. I have a
question about the formality tool from synopsis. If someone knows of a
better google group to post this message, please let me know.

The match and verify portion of formality's report sometimes reports
some "Unmatched unread points". Does anyone know what this means?

Thanks.

Hi,

An unread point is a point (mostly a register) that is not used by your
code. You might for instance compute a sum and register it but in the next
stage, you use only the most significant bits, so the least significant bits
become unread.
Unmatched means that Formality couldn't match it with a register in the
implementation design. Typically, this is because your synthesis tool has
removed the unread register (you can tell most tools to leave those
registers, but normally you don't want this).
So the real question is: did you expect the unread unmatched point(s) to be
unread? If so, all is fine, if not, check your code. Having said this, the
only place where this could matter is with some RAM BIST insertion flows
where cores might be inserted but only be connected later in the flow.

I hope this helped, if not, call your Formality FAE or check solvnet.

Regards,
Alvin Andries.

 

[WEEB]

BC is out of date and end-of-lifed. Look at products that use the
System C standard, i.e. from Forte Design Systems (www.forteds.com) or
Mentor Graphics(www.mentor.com) for behavioral synthesis. Which tool
depends on your target device platform. Mentor is more suited towards
FPGA design, whereas Forte is for design ASICs and SoCs. Forte is
adding FPGA support and Mentor is probably adding some ASIC capability.

chrisbw@gmail.com wrote:

It's not listed on Synopsys' product page. Is it EOL? Has BC
functionality been integrated into DC?

 

Hi Moises,
After you compile your design, you can see your design's RTL view. You
can select the net in the RTL view ,drag and drop the net in the SCOPE
constraints editor and specify the clock frequency. Hope this will help
you to solve your problem.

Regards,
Srini.

 

[Jogi]

isn't this an unwelcome crap? Could we block such messages?

Jogi
-----
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w)O>+<9UVS;F>qaGL<Uq#v`V6(F]- rM;$g+!4IIQ*827?H4

 

[pengdaimin]

You can use Cadence Signalstorm library characterization tool to create a
..lib file.Altough,you can use Mentor's tool Smart series tools about std
cell library.
wish this help!

 

[Harold]

Get a license of both tools and run SA versus DC
Getting up to speed with SA takes you a day
Getting up to speed with DC will take you weeks
SA run/compile time is a factor 5-10 times better
SA QoR is 10-15% better
SA can do 2M gates topdown!
Ask Cooley for feedback or ask Synplicity for customer references.


"Edison" <305liuzg@163.net> wrote in message news:<bcq0em$2g8b$1@mail.cn99.com>...

what is the difference between them.
can synplictiy asic do a good job in synthesis?

please give me a detail answer!
thanks a lot!

 

[Chenbo Liu]

I think there may be some sth. wrong before this step.
Check the settings.

Best,

Chenbo Liu

<vramamu@imap1.asu.edu> wrote in message
newsine.GSO.4.21.0307081248420.22639-100000@general2.asu.edu...
: hi,
: I am doing synthesis using synopsys using technology library lsi_10k,
: and when I do the post synthesis simulation using Cadence Nclaunch tool, i
get
: this error message during the elaboration part of the compilation..
:
: this is the error message that i get
: "
: ncelab: *E,DLENEW: Intermediate file package IEEE.VITAL_PRIMITIVES (AST)
: is newer than expected by architecture IEEE.OR2:VITAL (AST)
: "
:
:
: Any idea ??
: any help wud be rally appreciated..
:
: Thanks
:
: Vijaykumar Ramamurthi
: rvkumar@asu.edu
:

 

[Ajeetha Kumari]

Hi Vijay,
This is a classical problem in VHDL, any "design entity" that
uses a package must be compiled AFTER the package. In your case:

IEEE.VITAL_PRIMITIVES is a package

and another package named IEEE.OR2 uses this package. Now it looks
like VITAL_* has been compiled AFTER OR2, I have no idea of who sets
up your libraries, if you can, do a re-compile with the modified
order. Another solution would be to create your own IEEE lib - not a
preferred one though, let me know if you need more help.

HTH,
Ajeetha
http://www.noveldv.com

<vramamu@imap1.asu.edu> wrote in message news:<Pine.GSO.4.21.0307081248420.22639-100000@general2.asu.edu>...

hi,
I am doing synthesis using synopsys using technology library lsi_10k,
and when I do the post synthesis simulation using Cadence Nclaunch tool, i get
this error message during the elaboration part of the compilation..

this is the error message that i get
"
ncelab: *E,DLENEW: Intermediate file package IEEE.VITAL_PRIMITIVES (AST)
is newer than expected by architecture IEEE.OR2:VITAL (AST)
"


Any idea ??
any help wud be rally appreciated..

Thanks

Vijaykumar Ramamurthi
rvkumar@asu.edu

 

[Chenbo Liu]

Hell Henning,

Try this command:

set_cell_property dont_utilize true -lib library_name cell_names

You can find this command in Ambit doc.

Another way is to look up in AC_Shell and DC_Shell Command Equivalencies
Table.
Look up "set_dont_use" which is used in dc and get the equivalent command
for ac_shell.

Best,

Chenbo Liu



"Henning Bahr" <Henning.Bahr@ncl.ac.uk> wrote in message
news:8679149d.0307300350.672e4541@posting.google.com...
: Hi!
: How can I tell Ambit/PKS not to take a specific cell from the standard
: library. For instance, I don't want Ambit to use Scan FFs in my
: design.
:
: Thanks in advance,
: Henning

 

[Pacbell User]

"Muzaffer Kal" <kal@dspia.com> wrote in message
news:0hmfivcgbme70a11ugu9n69jkjnjjcdf7q@4ax.com...

On 30 Jul 2003 04:50:49 -0700, Henning.Bahr@ncl.ac.uk (Henning Bahr)
wrote:

Hi!
How can I tell Ambit/PKS not to take a specific cell from the standard
library. For instance, I don't want Ambit to use Scan FFs in my
design.

Thanks in advance,
Henning

set_cell_property dont_utilize true [find -cellref SDFF*]

I can't steal your thunder, so I'll just add a little whimper...

.... [find -cellref -register S* ]

Artisan's libraries have tons and tons of permuted flipflops,
some are 'SDFF', some are 'SEDFF..' Fortunately, all
the scanflops begin with 'S'. The -register option merely
ensures that only register-cells (flipflops) are returned.

 

[Prasanna]

"Pacbell User" <dont_reply@dont_reply.com> wrote in message news:<sSgXa.473$gC7.184@newssvr23.news.prodigy.com>...

"Muzaffer Kal" <kal@dspia.com> wrote in message
news:0hmfivcgbme70a11ugu9n69jkjnjjcdf7q@4ax.com...
On 30 Jul 2003 04:50:49 -0700, Henning.Bahr@ncl.ac.uk (Henning Bahr)
wrote:

Hi!
How can I tell Ambit/PKS not to take a specific cell from the standard
library. For instance, I don't want Ambit to use Scan FFs in my
design.

Thanks in advance,
Henning

set_cell_property dont_utilize true [find -cellref SDFF*]

I can't steal your thunder, so I'll just add a little whimper...

... [find -cellref -register S* ]

Artisan's libraries have tons and tons of permuted flipflops,
some are 'SDFF', some are 'SEDFF..' Fortunately, all
the scanflops begin with 'S'. The -register option merely
ensures that only register-cells (flipflops) are returned.

Correct me if I am wrong...

Synopsys knows which are scan cells by default in the library. If you
do a report lib then it shows attributes on each cell type it has (It
mentions which cells are scan cells). If you use compile -scan option
only then scan cells are inferred. dont_use is also an good useful
option if you know your library well.

- Prasanna