DesignRules:331 Dangling RAMB16A output: (Help)

R

rootz

Guest
Could someone explain why this warning appears when running
place-and-route on my design.

WARNING:DesignRules:332 - Blockcheck: Dangling RAMB16A output. Pin
DOPA0 of comp
MDBLOCK/MDFIFO/B345 is not connected.
WARNING:DesignRules:332 - Blockcheck: Dangling RAMB16A output. Pin
DOPA1 of comp
MDBLOCK/MDFIFO/B345 is not connected.
WARNING:DesignRules:332 - Blockcheck: Dangling RAMB16A output. Pin
DOPA2 of comp
MDBLOCK/MDFIFO/B345 is not connected.


It complains about a xilinx coregen component output port not being
connected. However, I donot find any problem in my verilog code.
Is this something I should be worried about

thanks
 
I doubt its Coregen doing something strange. The data width Coregen'ed
component (FIFO) was 65 bits wide. I am not sure if this has any effect
on the warnings
 
On 3 Feb 2005 11:16:23 -0800, "rootz" <kgyang@gmail.com> wrote:

I doubt its Coregen doing something strange. The data width Coregen'ed
component (FIFO) was 65 bits wide. I am not sure if this has any effect
on the warnings
Click to expand...
The number 65 is quite significant. This will use two 36 bit rams, so
a number of outputs (three on one ram and four on the other) will be
left floating (i.e. "Dangling"), hence the warnings.

To answer your original question: this is not something you should be
worried about.

Regards,
Allan
 
"rootz" <kgyang@gmail.com> wrote in message
news:1107446066.193678.171700@c13g2000cwb.googlegroups.com...
Could someone explain why this warning appears when running
place-and-route on my design.

WARNING:DesignRules:332 - Blockcheck: Dangling RAMB16A output. Pin
DOPA0 of comp
MDBLOCK/MDFIFO/B345 is not connected.
WARNING:DesignRules:332 - Blockcheck: Dangling RAMB16A output. Pin
DOPA1 of comp
MDBLOCK/MDFIFO/B345 is not connected.
WARNING:DesignRules:332 - Blockcheck: Dangling RAMB16A output. Pin
DOPA2 of comp
MDBLOCK/MDFIFO/B345 is not connected.


It complains about a xilinx coregen component output port not being
connected. However, I donot find any problem in my verilog code.
Is this something I should be worried about

thanks
Click to expand...
Don't worry. When the dual-port distributed CLB SelectRAMs are put in the
fabric, there are two devices created by your synthesis: the single-port
"half" of the memory and the dual-port "half." It's necessary in the
Spartan families but not necessarily required in the Virtex-II and later
devices in the Virtex line if I understand things right; the Virtex-II shows
that a dual-port can be implemented with A[4:1] and WG[4:1] lines into a LUT
without instantiating the single port "half" that *is* required in the
Spartan series and earlier Virtex parts.

If you are in the Virtex-II or later devices, you may have "trash" left in
your design that the synthesizer didn't need to instantiate and the Xilinx
software didn't remove but I don't expect those would affect your resource
usage significantly.

You might find further info in the Xilinx Answers Database.
 
On Thu, 03 Feb 2005 17:16:25 GMT, "John_H" <johnhandwork@mail.com>
wrote:

"rootz" <kgyang@gmail.com> wrote in message
news:1107446066.193678.171700@c13g2000cwb.googlegroups.com...
Could someone explain why this warning appears when running
place-and-route on my design.

WARNING:DesignRules:332 - Blockcheck: Dangling RAMB16A output. Pin
DOPA0 of comp
MDBLOCK/MDFIFO/B345 is not connected.
WARNING:DesignRules:332 - Blockcheck: Dangling RAMB16A output. Pin
DOPA1 of comp
MDBLOCK/MDFIFO/B345 is not connected.
WARNING:DesignRules:332 - Blockcheck: Dangling RAMB16A output. Pin
DOPA2 of comp
MDBLOCK/MDFIFO/B345 is not connected.


It complains about a xilinx coregen component output port not being
connected. However, I donot find any problem in my verilog code.
Is this something I should be worried about

thanks

Don't worry. When the dual-port distributed CLB SelectRAMs are put in the
fabric, there are two devices created by your synthesis: the single-port
"half" of the memory and the dual-port "half." It's necessary in the
Spartan families but not necessarily required in the Virtex-II and later
devices in the Virtex line if I understand things right; the Virtex-II shows
that a dual-port can be implemented with A[4:1] and WG[4:1] lines into a LUT
without instantiating the single port "half" that *is* required in the
Spartan series and earlier Virtex parts.

If you are in the Virtex-II or later devices, you may have "trash" left in
your design that the synthesizer didn't need to instantiate and the Xilinx
software didn't remove but I don't expect those would affect your resource
usage significantly.

You might find further info in the Xilinx Answers Database.
Click to expand...
The OP is actually using a block ram rather than a CLB ram. In this
case, the dangling outputs are the unused "parity" bits.

Note: the ram itself doesn't support parity; the 36 bit width of the
ram is arbitrarily described as being made up from 32 "data" bits and
4 "parity" bits.

It gives warnings for DOPA0, DOPA1 and DOPA2, but not DOPA3.
Presumably DOPA3 is actually connected to some part of the user's
design. This is possibly a bug, or maybe coregen is doing something
strange.

Perhaps the OP would like to provide more information. For example,
what data width was coregen asked to create? (Was it 37 bits?)

Regards,
Allan
 
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