Designing MUX with tri sate buffers in xilinx virtex II FPGA

[Oleg]

Hi everybody !
I read in an article that in FPGA there is a lot of tri state buffers
that are rarely used and when designing a large multiplexer its
bettere to take adventage of them to economize CLB's. But in this
article it was brefly approched. My question is : is it realy good to
use them from timing point of view ???. How to write a VHDL code for
using them ?? for example for MUX of 16:1 (--> select signal is of 4
bits )and each vector is of length of 4 bits.
Any help is appreciated, thanks.

 

[Ralf Hildebrandt]

Oleg wrote:

[tri-state muxes]

is it realy good to
use them from timing point of view ???.

The delay of a tri-state mux is everytime the delay of a tri-state
buffer - indipendent from mux-width.

But this hold only as long as every tri-state buffer is able to *drive*
this huge bus. If not, the synthesis tool tries to use the next bigger
tri-state buffer, that is able to drive stronger. If it does not finde
one, synthesis will "loop endlessly".

How to write a VHDL code for
using them ??

Every component, that is allowed to write to the bus gets a tri-state
buffer:

process(enableA,data_to_driveA)
begin
if (enableA='1') then
target_bus<=data_to_driveA;
else target_bus<=(others=>'Z');
end if;
end process;

For every component an enable-signal must exist. In no case more than
one component is allowed to drive to the target_bus. Everytime the bus
must be driven with some value - even, if no component wants to drive.
(Make a dummy driver.)

Note: target_bus must be a std_logic(_vector), because it needs to be
resolved.



Ralf

 

[Ray Andraka]

Huh??

The tristate buffers in Xilinx FPGAs are fixed assets. You can't change
the size. In Xilinx Virtex and SPartanII and later families, the
'tristate' is not a true tristate, rather it is a gating arrangement using
dedicated gates to mimic tristate from the user's point of view. The logic
has gotten progressively faster, and the number of tristates per logic cell
has decreased in every successive family to the point that in many cases
there is no advantage to using them. Indeed, in order to use them
effectively, you need to floorplan the TBUF locations so that the drivers
for each line all lie in the same row, and are on certain columns (the
connectivity is split into four sets that are rotated across columns). The
xilinx TBUFs do resolve multiple drivers, IIRC they resolve to low if any
driver is low.

They can either be instantiated by putting TBUF primitives in your design,
or by inference using 'Z's:

y<= d0 when sel="00" else (others=>'Z');
y<= d1 when sel="01" else (others=>'Z');
y<= d2 when sel="10" else (others=>'Z');
y<= d3 when sel="11" else (others=>'Z');


Ralf Hildebrandt wrote:

The delay of a tri-state mux is everytime the delay of a tri-state
buffer - indipendent from mux-width.

But this hold only as long as every tri-state buffer is able to *drive*
this huge bus. If not, the synthesis tool tries to use the next bigger
tri-state buffer, that is able to drive stronger. If it does not finde
one, synthesis will "loop endlessly".

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[Ralf Hildebrandt]

Ray Andraka wrote:

Huh??

The tristate buffers in Xilinx FPGAs are fixed assets. You can't change
the size.

I should mention, that my posting was not written for one specific
target. (I forgot to mention it - sorry.) I only answered to
VHDL-specific subquestions.

I just collected some facts about tri-state busses. (E.g. in standard
cell librarys often tri-state buffes with different driver strength exist.)


Ralf

 

[Ray Andraka]

The OP did explicitly state "...in FPGA there is a lot of tri state buffers
that are rarely used and when designing...". Your response had absolutely
nothing to do with the OP's questions, as your remarks do not pertain to
*any* FPGA.

Ralf Hildebrandt wrote:

I should mention, that my posting was not written for one specific
target. (I forgot to mention it - sorry.) I only answered to
VHDL-specific subquestions.

I just collected some facts about tri-state busses. (E.g. in standard
cell librarys often tri-state buffes with different driver strength exist.)

Ralf

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759