Design with IP-Cores on different FPGAs

Hi,

i'm trying to find a solution for the problem above. I have several
different FPGAs and one vhdl design with some core functions. Is it
possible to design the vhdl code in such a way that the FPGA could be
selected with a generic and depending on the selected FPGA the specific
IP Core is selected.

BR Stefan

 

[Mark McDougall]

sthauf@web.de wrote:

i'm trying to find a solution for the problem above. I have several
different FPGAs and one vhdl design with some core functions. Is it
possible to design the vhdl code in such a way that the FPGA could be
selected with a generic and depending on the selected FPGA the specific
IP Core is selected.

Yes, though I believe this is better off done with VHDL 'Configurations'
rather than generics.

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

 

[Ralf Hildebrandt]

sthauf@web.de wrote:

Is it
possible to design the vhdl code in such a way that the FPGA could be
selected with a generic and depending on the selected FPGA the specific
IP Core is selected.

Yes - You already have given the answer: if-generate or for-generate is
the solution.

gen_label_1 : if generic_param=1 generate
-- code for FPGA 1
end generate;

gen_label_2 : if generic_param=2 generate
-- code for FPGA 2
end generate;

-- and so on


In general VHDL could should be portable to any targets - ASIC and FPGA.
Unfortunately this is not possible every time (e.g. if one special macro
block of a FPGA has to be used).

=> Try to write as much as possible independent from the target. It
might be a good idea to not mix independent code blocks with
device-specific code blocks in one entity/architecture. (It would make
is easier to port to code to another target.)

Ralf

 

[sthauf@web.de]

Hi Ralf,

Thanks, I searched for that command. And it seams to work.

BR,
Stefan