design querres

[ashu]

i was synthesizing a test code of MINIMIPS from open cores

i was trying to compare the difference between gated clock and non gate
clock tecnhique

i was astonished to find that both area and leakge-power come down in
the gated clock implementation
when it should actually go up !! since we are adding more gates in the
gated clock approach
so ideally speaking my leakge power should go up and so should my area

what could be reason to due to it

 

[D Stanford]

ashu wrote:

i was synthesizing a test code of MINIMIPS from open cores

i was trying to compare the difference between gated clock and non gate
clock tecnhique

What do you mean by " gated clock" and "non gate clock" ?

 

[ashu]

gated clock is technique where one can insert few more gates to reduce
activity
for example in a 4bit counter the LSB is swtiched every clock cycle
but the higher order bits are not swtiched that often
so there is no need to clock them ....every clock cycle ...so we insert
a gate in between
which says when the intermediate signal makes a transistion then only
clock the more significant bit gates

this can be implemented by an option in synopsys

swtiched not so often
D Stanford wrote:

ashu wrote:
i was synthesizing a test code of MINIMIPS from open cores

i was trying to compare the difference between gated clock and non gate
clock tecnhique

What do you mean by " gated clock" and "non gate clock" ?

 

[Ben Jones]

"ashu" <ashutosh.ghildiyal@gmail.com> wrote in message
news:1149774645.094736.138370@c74g2000cwc.googlegroups.com...

i was trying to compare the difference between gated clock and non gate
clock tecnhique
i was astonished to find that both area and leakge-power come down in
the gated clock implementation

Not very astonishing. That's why ASICs often use gated clocks.

Instead of having extra transistors in every flip-flop to
clock-enable/disable individual register elements in the design, the clock
nets are directly gated. This not only allows all the synchronous elements
to be stopped from toggling at once, but it reduces the power dissipation on
the clock lines too.

When some core has an option of gated vs. non gated, it's usually so you can
put it on an FPGA (where gated clocks are Not A Good Idea) or an ASIC (where
it might save you some area/power).

-Ben-

 

[Andy]

Xilinx FPGA (I don't know about others) clock buffers have enables that
safely, synchronously enable and disable the clock, and therefore can
be safely used to "gate" the clock. Just like global clock buffers
though, they are limited in quantitiy, so pervasive clock gating is
discouraged in FPGA design. Generally, you have to have to replace a
lot of clock-enabled flops with a gated clock before you will see much
benefit in power savings on an FPGA.

Andy


Ben Jones wrote:

"ashu" <ashutosh.ghildiyal@gmail.com> wrote in message
news:1149774645.094736.138370@c74g2000cwc.googlegroups.com...
i was trying to compare the difference between gated clock and non gate
clock tecnhique
i was astonished to find that both area and leakge-power come down in
the gated clock implementation

Not very astonishing. That's why ASICs often use gated clocks.

Instead of having extra transistors in every flip-flop to
clock-enable/disable individual register elements in the design, the clock
nets are directly gated. This not only allows all the synchronous elements
to be stopped from toggling at once, but it reduces the power dissipation on
the clock lines too.

When some core has an option of gated vs. non gated, it's usually so you can
put it on an FPGA (where gated clocks are Not A Good Idea) or an ASIC (where
it might save you some area/power).

-Ben-

 

[ashu]

thanks ben and andy
so the power goes down beacuse the clock nets are gated and hence power
dissipation on clock lines goes down
this is fine for power reduction but why is the area going down ?
Andy wrote:

Xilinx FPGA (I don't know about others) clock buffers have enables that
safely, synchronously enable and disable the clock, and therefore can
be safely used to "gate" the clock. Just like global clock buffers
though, they are limited in quantitiy, so pervasive clock gating is
discouraged in FPGA design. Generally, you have to have to replace a
lot of clock-enabled flops with a gated clock before you will see much
benefit in power savings on an FPGA.

Andy


Ben Jones wrote:
"ashu" <ashutosh.ghildiyal@gmail.com> wrote in message
news:1149774645.094736.138370@c74g2000cwc.googlegroups.com...
i was trying to compare the difference between gated clock and non gate
clock tecnhique
i was astonished to find that both area and leakge-power come down in
the gated clock implementation

Not very astonishing. That's why ASICs often use gated clocks.

Instead of having extra transistors in every flip-flop to
clock-enable/disable individual register elements in the design, the clock
nets are directly gated. This not only allows all the synchronous elements
to be stopped from toggling at once, but it reduces the power dissipation on
the clock lines too.

When some core has an option of gated vs. non gated, it's usually so you can
put it on an FPGA (where gated clocks are Not A Good Idea) or an ASIC (where
it might save you some area/power).

-Ben-