design kits for virtuoso 6.1

T

Taimur

Guest
Does someone know a process design kit that works FINE with virtuoso
6.1? The ncsu 1.6 has a lot of bugs and limitations. I'm talking about
a design kit that has the same resources that gpdk090 and gpdk180
have. Does someone know how to get the Generic StdCell lib 090 and 180
(gsclib090 and gsclib180) ? Thanks in advance.
 
On May 24, 9:49 am, Taimur <taimurgib...@gmail.com> wrote:
Does someone know a process design kit that works FINE with virtuoso
6.1? The ncsu 1.6 has a lot of bugs and limitations. I'm talking about
a design kit that has the same resources that gpdk090 and gpdk180
have. Does someone know how to get the Generic StdCell lib 090 and 180
(gsclib090 and gsclib180) ? Thanks in advance.
Click to expand...
What is the ncsu 1.6 and gpdk090, or maybe I should ask whose are
those or where do those pdk's come from? Don't the foundries provide
for that? I remember MOSIS had certain resources for the universities.
 
On May 24, 6:45 pm, vlsidesign <ford...@gmail.com> wrote:
On May 24, 9:49 am, Taimur <taimurgib...@gmail.com> wrote:

Does someone know a process design kit that works FINE with virtuoso
6.1? The ncsu 1.6 has a lot of bugs and limitations. I'm talking about
a design kit that has the same resources that gpdk090 and gpdk180
have. Does someone know how to get the Generic StdCell lib 090 and 180
(gsclib090 and gsclib180) ? Thanks in advance.

What is the ncsu 1.6 and gpdk090, or maybe I should ask whose are
those or where do those pdk's come from? Don't the foundries provide
for that? I remember MOSIS had certain resources for the universities.
Click to expand...
Every foundry provide a design kit. This is the most basic thing to
make possible to design a chip. But, when Cadence upgrade Virtuoso
from 5.1 to 6.1, they change the design database type: cdb to OA.
OpenAcess is a database type that aims to ease the sharing of data
between softwares of diferent vendors. But the foundries did't upgrade
they design kits yet. I heard about TSMC and the HIT-KIT for 0.35um
are being upgrated.

NCSU is a free design kit provided by North Carolina State University
to the processes that MOSIS provide.

GPDK090 is a cadence proprietary "generic" design kit. Generic means
it is not applicable to any process. It exists for learning purposes
only.
 
Hi Taimur,

In an industrial context where chips are designed to make money, the
foundry/process/Pdk is something we think about before starting any
development. We can't just ask to move with another foundry when some
bugs in the flow are encountered :-( I understand this is not a
problem when you design Soft chips/Ips in case of a University
projects when generic PDks could be used.

Well, What I would like to advice is rather to report these bugs/
limitations to your PDK provider. I'm pretty much sure they will be
doing their hardest to make it working fine for you. That's the best
way of improving things. Switching PDKs/Vendors, even in a Scholar
context, is not the ideal solution since you'll waste a bit of time in
porting your already designed blocks which is not that easy ...

And BTW, I have never ever known a bug-free PDK, please let me know
should you find someone ;-)

Good luck anyway
 
Taimur schrieb:
Does someone know a process design kit that works FINE with virtuoso
6.1? The ncsu 1.6 has a lot of bugs and limitations. I'm talking about
a design kit that has the same resources that gpdk090 and gpdk180
have. Does someone know how to get the Generic StdCell lib 090 and 180
(gsclib090 and gsclib180) ? Thanks in advance.
Click to expand...
Have you looked at the generic 130nm proof of concept library from
the IPL Alliance (www.iplnow.com) ?
This library is included in the CiraNova PyCell Studio for and
works fine with Virtuoso (www.ciranova.com).

Yours,

Martin Heller

- not speaking for FhG ISIT -
 
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