Design Flow: STA to Synthesis

[Crimson_M]

Is anyone familiar with Mentor Graphics tools? I am currently using
ModelSim 5.5e at school. After I have compiled and functionally
verified my VHDL design I would like to synthesize my HDL description
into a transistor level design. From there I would like to perform a
more detailed timing and power analysis using some standard cell
libraries.

Is this possible?

In the past I have used Cadence's design tools, namely Virtuoso for
layout and schematic level. Is it possible with today's automated
design software to transform a HDL description into a transistor level
description, say, fit for Cadence or other CAD tools? If so, please
list product vendors/names. I would greatly appreciate any help, as I
am only experienced with VHDL compilation/simulation.

-Brandon

 

[Brian Drummond]

On 8 Sep 2003 13:36:22 -0700, crimson_m@hotmail.com (Crimson_M) wrote:

Is anyone familiar with Mentor Graphics tools? I am currently using
ModelSim 5.5e at school. After I have compiled and functionally
verified my VHDL design I would like to synthesize my HDL description
into a transistor level design. From there I would like to perform a
more detailed timing and power analysis using some standard cell
libraries.

Is this possible?

Yes ... but probably for a price, using standard cell technology.

Using FPGA, you can do it at a much lower price (including free). Since
you talk about school, I'll assume this is important, and refer to
Xilinx FPGAs.

In the past I have used Cadence's design tools, namely Virtuoso for
layout and schematic level. Is it possible with today's automated
design software to transform a HDL description into a transistor level
description, say, fit for Cadence or other CAD tools? If so, please
list product vendors/names. I would greatly appreciate any help, as I
am only experienced with VHDL compilation/simulation.

After simulation (the design now works, right?) you synthesise ... not
quite down to the transistor level, but to whatever low-level primitive
circuit functions your technology vendor supports, as a netlist in EDIF
format. For Xilinx, that would typically be 4-input lookup tables
(implementing any 4-input logic function) and flip-flops, and a few
others.

Synthesis tools: Xilinx Webpack (_big_ free download - www.xilinx.com )
or Mentor Leonardo (now Precision Synthesis) or Synplify - the latter
two are fairly big money. Leonardo (some versions) can plug in other
technology libraries, including some standard cell libraries.

Following this, the EDIF netlist is mapped, (optionally floorplanned, if
you want to control circuit placement for better performance), placed
and routed, to the target chip. The complete circuit can now be written
out in VHDL as a gate-level netlist, annotated with timing information
in a separate .SDF file. (Tools: Xilinx Webpack again or Xilinx
Alliance. Specific to that manufacturer's technology, obviously!)

These two files (.vhd and .sdf) can be loaded into Modelsim for
simulation. If your I/O ports are std_logic[_vector] (as opposed to
signed/unsigned or anything fancier) the .vhd can drop straight into the
same testbench you used for the original simulation.

Now you have timing simulations. Power is another matter ... look at
Xilinx website for XPower power estimation software, which (I think)
interacts with Modelsim simulation results.

Plus ... unlike standard cell ... if you targeted the right chip, you
can run the finished design on a low-cost demo board - Insight or
www.xess.com come to mind.

Alternatively, there are other FPGA manufacturers such as Altera
( www.altera.com ) with basically similar tool chains, or you may have
access to some standard cell technology from school.

- Brian