design flow questions

I am learning IC design with VHDL and have following questions.
Appreciate if anyone can clarify the following

After the design is synthesized I get the following files.
Alter Quartus II : .sdo and .vho
Actel Libero (Synplify) : .sdf, .vhm and .edn

What is the significance of these files and how are they used further
in the design flow?

Altera QuartusII has generated .sdo and .vho files for post synthesis
simulation for modelsim but I don't see any references to the .sdo
file from .vho file. How do we use these two files together in
modelsim for post synthesis simulation?

What are VITAL libraries? Where and How I use them as part of the
design flow? Do I need to use them as part of VHDL coding during
design or tools do that later? Are they required for both FPGA and
ASIC design flows and why?

I am stuck here and not able to move forward. I would really
appreciate if explained in detail.

Thanks in advance.

 

I would really appreciate if someone clarifies, particularly VITAl
part.

On May 24, 4:48 pm, bhavanire...@gmail.com wrote:

I am learning IC design with VHDL and have following questions.
Appreciate if anyone can clarify the following

After the design is synthesized I get the following files.
Alter Quartus II : .sdo and .vho
Actel Libero (Synplify) : .sdf, .vhm and .edn

What is the significance of these files and how are they used further
in the design flow?

Altera QuartusII has generated .sdo and .vho files for post synthesis
simulation for modelsim but I don't see any references to the .sdo
file from .vho file. How do we use these two files together in
modelsim for post synthesis simulation?

What are VITAL libraries? Where and How I use them as part of the
design flow? Do I need to use them as part of VHDL coding during
design or tools do that later? Are they required for both FPGA and
ASIC design flows and why?

I am stuck here and not able to move forward. I would really
appreciate if explained in detail.

Thanks in advance.

 

[Paul Uiterlinden]

bhavanireddy@gmail.com wrote:

I would really appreciate if someone clarifies, particularly VITAl
part.

Description "stolen" from
http://ieeexplore.ieee.org/Xplore/login.jsp?url=/iel3/4438/12592/00580410.pdf?arnumber=580410

"In a VHDL-based design flow for application specific integrated circuits,
VITAL provides a uniform methodology for developing ASIC libraries for
signoff simulation. The VITAL Standard includes specialized routines for
describing behavior and timing of ASIC cells and integrates backannotation
via Standard Delay Format (SDF). One of the key issues of the VITAL
initiative was to accelerate simulation performance at gate level by
allowing only a restricted set of VHDL."

I've never used VITAL. In my experience, gate level netlist simulation is
best done (if it must be done anyway) using a Verilog netlist with an SDF
file. It poses less problems than writing out a VHDL netlist and generally
is faster.

--
Paul Uiterlinden
www.aimvalley.nl
e-mail addres: remove the not.

 

Thanx paul. So VITAL routines come into picture only for ASIC targets
but not for FPGAs. Please correct me if my understanding is wrong.

Description "stolen" fromhttp://ieeexplore.ieee.org/Xplore/login.jsp?url=/iel3/4438/12592/0058...

"In a VHDL-based design flow for application specific integrated circuits,
VITAL provides a uniform methodology for developing ASIC libraries for
signoff simulation. The VITAL Standard includes specialized routines for
describing behavior and timing of ASIC cells and integrates backannotation
via Standard Delay Format (SDF). One of the key issues of the VITAL
initiative was to accelerate simulation performance at gate level by
allowing only a restricted set of VHDL."

I've never used VITAL. In my experience, gate level netlist simulation is
best done (if it must be done anyway) using a Verilog netlist with an SDF
file. It poses less problems than writing out a VHDL netlist and generally
is faster.

--
Paul Uiterlindenwww.aimvalley.nl
e-mail addres: remove the not.

 

[Mike Treseler]

bhavanireddy@gmail.com wrote:

So VITAL routines come into picture only for ASIC targets
but not for FPGAs. Please correct me if my understanding is wrong.

sdf is a file format for gate delay information.
verilog can use it directly
vhdl requires a library called VITAL to use it.
none of this is needed for a functional sim.
read chapter 8
http://www.it.lth.se/courses/dsi/material/Labs/ee_manual.pdf

google is your friend

-- Mike Treseler