Design entries for FSM

[Sue]

Does anyone know how can one enter FSM in Xilinx sysnthesis tool.
I have a FSM in a text format called the kiss2 format.
It looks something like this:

file input.kiss2
--------------------------------------------start of
file---------------------------
..i 2
..o 2
..p 8
..s 4
01 s0 s1 11
11 so s3 00
01 s1 s0 11
11 s1 s2 00
1- s2 s3 01
0- s2 s1 10
11 s3 s0 10
10 s3 s2 11
--------------------------------------------end of
file---------------------------------
i= # of inputs
o= # of outputs
p= # of transitions
s= # of states
01 so s1 11 = this is read as for input 01 and current state s0 the
output is 11 and next state is s1.
'-' means don't care


Does anyone know a way in which I can convert this to a format such
that it can be entered into the Xilinx synthesis tool and I can get
the FSM synthesized for further use my implementation

 

[KJ]

"Sue" <sudhangi@gmail.com> wrote in message
news:c1da0a24-3166-4ad6-aff9-bab40f8214f6@s37g2000prg.googlegroups.com...

Does anyone know how can one enter FSM in Xilinx sysnthesis tool.
I have a FSM in a text format called the kiss2 format.
It looks something like this:

snip

Does anyone know a way in which I can convert this to a format such
that it can be entered into the Xilinx synthesis tool and I can get
the FSM synthesized for further use my implementation

Other than the obvious approach of converting it to either of the accepted
standards like VHDL or Verilog?

Or is the problem that you don't understand the kiss2 format and therefore
how to translate it?

Kevin Jennings