Design Engineering Exercise of the Week

[Jim Thompson]

Young (and old) engineers interested in honing their talents are
invited to examine.........

http://www.analog-innovations.com/SED/MC1552LookAlike.pdf

which is a workup of my old MC1552 design (from the '60's) but using
discrete transistors.

As a first exercise calculate the output DC bias point... by hand
please... solutions by simulation will be ignored.

If you think that is harsh, keep in mind that I did this design when I
was around 25 years old, and did ALL the design work on a pad of
paper.

(We'll attack the AC analysis later.)

Enjoy!

(If I have the time I will try to keep you exercised (or is it
exorcised ? about every week or so.)

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

 

[Fred Bloggs]

Jim Thompson wrote:

Young (and old) engineers interested in honing their talents are
invited to examine.........

http://www.analog-innovations.com/SED/MC1552LookAlike.pdf

which is a workup of my old MC1552 design (from the '60's) but using
discrete transistors.

As a first exercise calculate the output DC bias point... by hand
please... solutions by simulation will be ignored.

If you think that is harsh, keep in mind that I did this design when I
was around 25 years old, and did ALL the design work on a pad of
paper.

(We'll attack the AC analysis later.)

Enjoy!

(If I have the time I will try to keep you exercised (or is it
exorcised ? about every week or so.)

...Jim Thompson

Well- there is a BIG difference between analysis and synthesis- and the
output bias comes out fairly easily by noting Vc2=Vb3=Vbe3~0.6V. This
makes Ic2=(6-0.6)/9.1k=0.6mA and also fixes Vbe2~0.6V too, and there is
a fairly huge corrective DC negative feedback loop locking the circuit
in. Vout is level shifted down by the Q6 current source working thru
R9=3K and applied to Q2 base, the Q6 current is ~(6-1.3)/6K so the level
shift is -(6-1.3)*3/6 or -2.35V. Now the collector current Ic1 can be
solved by equating the loop equations so that Vbe2=0.6V. On the emitter
side of Q2 you have Ve2=(0.6mA*0.91+Ic1*0.065)*75 due to current divider
action on Ie2 and Ie1; and on the base side you have Vb2=Vout-2.35 where
Vout=6-Ic1*510-Vbe7. Since Ic7~9xIc2, take Vb7=0.6+0.026*Ln(9)=0.66V.
Then Vbe2=0.6V=Vb2-Ve2=(6-Ic1*510-0.66-2.35)-(0.6mA*0.93+Ic1*0.065)*75.
Solve this for Ic1=4.6mA, making Vout=6-4.54mA*510-0.66=3.0V.

 

[Jim Thompson]

On Fri, 02 Jan 2004 12:42:10 GMT, Fred Bloggs <nospam@nospam.com>
wrote:

Jim Thompson wrote:
Young (and old) engineers interested in honing their talents are
invited to examine.........

http://www.analog-innovations.com/SED/MC1552LookAlike.pdf

which is a workup of my old MC1552 design (from the '60's) but using
discrete transistors.

As a first exercise calculate the output DC bias point... by hand
please... solutions by simulation will be ignored.

If you think that is harsh, keep in mind that I did this design when I
was around 25 years old, and did ALL the design work on a pad of
paper.

(We'll attack the AC analysis later.)

Enjoy!

(If I have the time I will try to keep you exercised (or is it
exorcised ? about every week or so.)

...Jim Thompson

Well- there is a BIG difference between analysis and synthesis- and the
output bias comes out fairly easily by noting Vc2=Vb3=Vbe3~0.6V. This
makes Ic2=(6-0.6)/9.1k=0.6mA and also fixes Vbe2~0.6V too, and there is
a fairly huge corrective DC negative feedback loop locking the circuit
in. Vout is level shifted down by the Q6 current source working thru
R9=3K and applied to Q2 base, the Q6 current is ~(6-1.3)/6K so the level
shift is -(6-1.3)*3/6 or -2.35V. Now the collector current Ic1 can be
solved by equating the loop equations so that Vbe2=0.6V. On the emitter
side of Q2 you have Ve2=(0.6mA*0.91+Ic1*0.065)*75 due to current divider
action on Ie2 and Ie1; and on the base side you have Vb2=Vout-2.35 where
Vout=6-Ic1*510-Vbe7. Since Ic7~9xIc2, take Vb7=0.6+0.026*Ln(9)=0.66V.
Then Vbe2=0.6V=Vb2-Ve2=(6-Ic1*510-0.66-2.35)-(0.6mA*0.93+Ic1*0.065)*75.
Solve this for Ic1=4.6mA, making Vout=6-4.54mA*510-0.66=3.0V.

Why don't you give me a general equation set rather than a
simulator-like numeric answer?

Then it will make sense to the student as to how the low TC comes
about.

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

 

[Fred Bloggs]

Jim Thompson wrote:

On Fri, 02 Jan 2004 12:42:10 GMT, Fred Bloggs <nospam@nospam.com
wrote:



Jim Thompson wrote:

Young (and old) engineers interested in honing their talents are
invited to examine.........

http://www.analog-innovations.com/SED/MC1552LookAlike.pdf

which is a workup of my old MC1552 design (from the '60's) but using
discrete transistors.

As a first exercise calculate the output DC bias point... by hand
please... solutions by simulation will be ignored.

If you think that is harsh, keep in mind that I did this design when I
was around 25 years old, and did ALL the design work on a pad of
paper.

(We'll attack the AC analysis later.)

Enjoy!

(If I have the time I will try to keep you exercised (or is it
exorcised ? about every week or so.)

...Jim Thompson

Well- there is a BIG difference between analysis and synthesis- and the
output bias comes out fairly easily by noting Vc2=Vb3=Vbe3~0.6V. This
makes Ic2=(6-0.6)/9.1k=0.6mA and also fixes Vbe2~0.6V too, and there is
a fairly huge corrective DC negative feedback loop locking the circuit
in. Vout is level shifted down by the Q6 current source working thru
R9=3K and applied to Q2 base, the Q6 current is ~(6-1.3)/6K so the level
shift is -(6-1.3)*3/6 or -2.35V. Now the collector current Ic1 can be
solved by equating the loop equations so that Vbe2=0.6V. On the emitter
side of Q2 you have Ve2=(0.6mA*0.91+Ic1*0.065)*75 due to current divider
action on Ie2 and Ie1; and on the base side you have Vb2=Vout-2.35 where
Vout=6-Ic1*510-Vbe7. Since Ic7~9xIc2, take Vb7=0.6+0.026*Ln(9)=0.66V.
Then Vbe2=0.6V=Vb2-Ve2=(6-Ic1*510-0.66-2.35)-(0.6mA*0.93+Ic1*0.065)*75.
Solve this for Ic1=4.6mA, making Vout=6-4.54mA*510-0.66=3.0V.


Why don't you give me a general equation set rather than a
simulator-like numeric answer?

Then it will make sense to the student as to how the low TC comes
about.

...Jim Thompson

The equations would look something like this- but there is a big factor
of 5 discrepancy with the simulated tempco:
Please view in a fixed-width font such as Courier.







V+ -Vbe3
Vbe2= V Ln(-------- )
T R I
7 eo2



V+ -Vout - Vbe7
Ic1= ---------------
R
5


V+ - 2Vbe,8,5
Ic6= --------------
R + R
8 10



=>


V+ - 2Vbe,8,5 V+ -Vbe3 V+ -Vout - Vbe7
Vout - R x--------- -( 0.93 x -------- +0.075x ---------------)x75
9 R + R R R
8 10 7 5


V+ -Vbe3
= V Ln(-------- ) =Vbe2
T R I
7 eo2




V+ - 2Vbe
or Vout= R x --------- + Vbe2 = V+/2 for R = 1/2 ( R + R )
9 R + R 9 8 10
8 10


=>


2xR
d Vout 0.075 x 75 9 0.93x75 d Vbe2
------ x (1+ ----------)= -(------- + ------ -1)x -----
d T R R + R R d T
5 8 10 7


0.075x75 d Vbe7
- -------- x -----
R d T
5





=> d Vout
------ = +40uV/oC <-- a factor of 5 better than simulation
d T

 

[Jim Thompson]

On Fri, 02 Jan 2004 17:05:53 GMT, Fred Bloggs <nospam@nospam.com>
wrote:

Jim Thompson wrote:
On Fri, 02 Jan 2004 12:42:10 GMT, Fred Bloggs <nospam@nospam.com
wrote:



Jim Thompson wrote:

Young (and old) engineers interested in honing their talents are
invited to examine.........

http://www.analog-innovations.com/SED/MC1552LookAlike.pdf

which is a workup of my old MC1552 design (from the '60's) but using
discrete transistors.

As a first exercise calculate the output DC bias point... by hand
please... solutions by simulation will be ignored.

If you think that is harsh, keep in mind that I did this design when I
was around 25 years old, and did ALL the design work on a pad of
paper.

(We'll attack the AC analysis later.)

Enjoy!

(If I have the time I will try to keep you exercised (or is it
exorcised ? about every week or so.)

...Jim Thompson

Well- there is a BIG difference between analysis and synthesis- and the
output bias comes out fairly easily by noting Vc2=Vb3=Vbe3~0.6V. This
makes Ic2=(6-0.6)/9.1k=0.6mA and also fixes Vbe2~0.6V too, and there is
a fairly huge corrective DC negative feedback loop locking the circuit
in. Vout is level shifted down by the Q6 current source working thru
R9=3K and applied to Q2 base, the Q6 current is ~(6-1.3)/6K so the level
shift is -(6-1.3)*3/6 or -2.35V. Now the collector current Ic1 can be
solved by equating the loop equations so that Vbe2=0.6V. On the emitter
side of Q2 you have Ve2=(0.6mA*0.91+Ic1*0.065)*75 due to current divider
action on Ie2 and Ie1; and on the base side you have Vb2=Vout-2.35 where
Vout=6-Ic1*510-Vbe7. Since Ic7~9xIc2, take Vb7=0.6+0.026*Ln(9)=0.66V.
Then Vbe2=0.6V=Vb2-Ve2=(6-Ic1*510-0.66-2.35)-(0.6mA*0.93+Ic1*0.065)*75.
Solve this for Ic1=4.6mA, making Vout=6-4.54mA*510-0.66=3.0V.


Why don't you give me a general equation set rather than a
simulator-like numeric answer?

Then it will make sense to the student as to how the low TC comes
about.

...Jim Thompson

The equations would look something like this- but there is a big factor
of 5 discrepancy with the simulated tempco:
Please view in a fixed-width font such as Courier.







V+ -Vbe3
Vbe2= V Ln(-------- )
T R I
7 eo2



V+ -Vout - Vbe7
Ic1= ---------------
R
5


V+ - 2Vbe,8,5
Ic6= --------------
R + R
8 10



=


V+ - 2Vbe,8,5 V+ -Vbe3 V+ -Vout - Vbe7
Vout - R x--------- -( 0.93 x -------- +0.075x ---------------)x75
9 R + R R R
8 10 7 5


V+ -Vbe3
= V Ln(-------- ) =Vbe2
T R I
7 eo2




V+ - 2Vbe
or Vout= R x --------- + Vbe2 = V+/2 for R = 1/2 ( R + R )
9 R + R 9 8 10
8 10


=


2xR
d Vout 0.075 x 75 9 0.93x75 d Vbe2
------ x (1+ ----------)= -(------- + ------ -1)x -----
d T R R + R R d T
5 8 10 7


0.075x75 d Vbe7
- -------- x -----
R d T
5





=> d Vout
------ = +40uV/oC <-- a factor of 5 better than simulation
d T

It's most likely Beta/hfe/BF... that is, non-zero base currents
everywhere.

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

 

[Paul Burridge]

On Fri, 02 Jan 2004 10:14:38 -0700, Jim Thompson
<invalid@invalid.invalid> wrote:

V+ -Vbe3
Vbe2= V Ln(-------- )
T R I
7 eo2



V+ -Vout - Vbe7
Ic1= ---------------
R
5


V+ - 2Vbe,8,5
Ic6= --------------
R + R
8 10



=


V+ - 2Vbe,8,5 V+ -Vbe3 V+ -Vout - Vbe7
Vout - R x--------- -( 0.93 x -------- +0.075x ---------------)x75
9 R + R R R
8 10 7 5


V+ -Vbe3
= V Ln(-------- ) =Vbe2
T R I
7 eo2




V+ - 2Vbe
or Vout= R x --------- + Vbe2 = V+/2 for R = 1/2 ( R + R )
9 R + R 9 8 10
8 10


=


2xR
d Vout 0.075 x 75 9 0.93x75 d Vbe2
------ x (1+ ----------)= -(------- + ------ -1)x -----
d T R R + R R d T
5 8 10 7


0.075x75 d Vbe7
- -------- x -----
R d T
5

You 3 useless bastards know *fuck all* about this kind of problem
solving. You make everything far more difficult than it needs to be in
some sort of pathetic attempt to make yourselves look clever.
Here's the proper way to go about solving this dipshit problem:

100dBX6'X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45=90.05% (at 50Khz).
1000dBX3'X2pi*2arc.tan/7pi*3sqrt!37/4piR^3+^2loge45100dBX6'dx/dy(42wpifL2)
X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45100dBX
6'X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45100dBX6'
X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45
100dBX6'X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45=90.05% (at 500Khz).
1000dBX3'X2pi*2arc.tan/7pi*3sqrt!37/4piR^3+^2loge45100dBX6'dx/dy(42wpifL2)
X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45100dBX

Simplifying:

2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45100dBX*factorial1024>>1
6'X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45100dBX6'
X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45
100dBX6'X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45=90.05% (at 50Khz).
1000dBX3'X2pi*2arc.tan/7pi*3sqrt!37/4piR^3+^2loge45100dBX6'dx/dy(42wpifL2)
X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45100dBX
6'X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45100dBX6'
X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45
100dBX6'X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45=90.05% (at 50Ehz).
800dBX3'X2pi*2arc.tan/7pi*3sqrt!37/4piR^3+^2loge45100dBX6'dx/dy(42wpifL2)
X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45100dBX

Solving for x:

2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45
100dBX6'X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45=90.05% (at 50Khz).
1000dBX3'X2pi*2arc.tan/7pi*3sqrt!37/4piR^3+^2loge45100dBX6'dx/dy(42wpifL2)
X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45100dBX
6'X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45100dBX6'
1000dBX3'X2pi*2arc.tan/7pi*3sqrt!37/4piR^3+^2loge45100dBX6'dx/dy(42wpifL2)
X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45100dBX
6'X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45100dBX6'
X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45
100dBX6'X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45=90.05% (at 50Ehz).

Resulting in:

4pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45100dBX*factorial1024>>1
6'X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45100dBX6'
X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45
100dBX6'X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45=90.05% (at 50Thz).
1030dBX3'X2pi*2arc.tan/7pi*3sqrt!37/4piR^3+^2loge45100dBX6'dx/dy(42wpifL2)
X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45100dBX
6'X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45100dBX6'
X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45
100dBX6'X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45=90.05% (at 50Mhz).
1070dBX3'X2pi*2arc.tan/7pi*3sqrt!37/4piR^3+^2loge45100dBX6'dx/dy(42wpifL2)
X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+bollocks^2
loge45100dBX100dBX6'X2pi*2arc.tan/3pi*3

Solving for y:

sqrt!37/4piR^3+^2loge45=90.05% (at 50Khz).
1000dBX3'X2pi*2arc.tan/7pi*3sqrt!37/4piR^3+^2loge45100dBX6'dx/dy(42wpifL2)
X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45100dBX
6'X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45100dBX6'
X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+(^2loge458474664*-4564)
100dBX6'X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45=90.05% (at 50Ghz).
1200dBX3'X2pi*2arc.tan/7pi*3sqrt!37/4piR^3+^2loge45100dBX6'dx/dy(42wpifL2)
X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45100dBX
6'X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45100dBX6'
X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45
100dBX6'X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45=90.05% (at 50Khz).
100dBX3'X2pi*2arc.tan/7pi*3sqrt!37/4piR^3+^2loge45100dBX6'dx/dy(42wpifL2)
X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45100dBX=10,000KW

The total precipitive reciprocal integral differential loss being
found by:

2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45100dBX*factorial1024>>1
6'X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45100dBX6'
X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45
100dBX6'X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45=90.05% (at
500GKhz).
108dBX3'X2pi*2arc.tan/7pi*3sqrt!37/4piR^3+^2loge45100dBX6'dx/dy(42wpifL2)
X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^3loge45100dBX
6'X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45100dBX6'
X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45
100dBX6'X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45=90.05% (at 50mhz).
1500dBX3'X2pi*2arc.tan/7pi*3sqrt!37/4piR^3+^2loge45100dBX6'dx/dy(42wpifL2)
X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^4loge45100dBX6'X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45100dBX6'
X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^7loge45
100dBX6'X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge45=90.05% (at
50000Ghz).
1009dBX3'X2pi*2arc.tan/7pi*3sqrt!37/4piR^3+^2loge45100dBX6'dx/dy(2wpifL2)
X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+^2loge35100dBX29_3.141592654*299792458M/s

There you go. Even *I* managed it in under 10 minutes. Big fucking
deal.


--

"I expect history will be kind to me, since I intend to write it."
- Winston Churchill

 

[Jackson Harvey]

Paul Burridge wrote:

(SNIP)

X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+bollocks^2

(SNIP)

I'm having some difficulty with this step. Can you give me a reference
to this bollocks function? I always seem to make a mess of every
equation that has this function.

Jackson Harvey

 

[Jim Thompson]

On Fri, 02 Jan 2004 15:47:39 -0600, Jackson Harvey
<jharvey@bermai.com> wrote:

Paul Burridge wrote:

(SNIP)

X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+bollocks^2

(SNIP)

I'm having some difficulty with this step. Can you give me a reference
to this bollocks function? I always seem to make a mess of every
equation that has this function.

Jackson Harvey

Aha! I see that Paul, the village idiot, has returned.

Please refrain from quoting him... help keep my PLONK effective.

Thanks!

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

 

[Tom Del Rosso]

In news:r7obvvge9981tishu28oviavejtq1haeqd@4ax.com,
Paul Burridge typed:

You 3 useless bastards know *fuck all* about this kind of problem
solving. You make everything far more difficult than it needs to be in
some sort of pathetic attempt to make yourselves look clever.
Here's the proper way to go about solving this dipshit problem:

"I've never known a newsgroup like it for people flying off the handle
over next to nothing."

X2pi*2arc.tan/3pi*3sqrt!37/4piR^3+bollocks^2

And then a miracle occurs?



--
-Reply in group, but if emailing add 2 more zeros-
-and remove the obvious-

 

[Tim Williams]

"Jim Thompson" <invalid@invalid.invalid> wrote in message
news:u889vv0jpmh7tv14oqjvsataucv6g56fok@4ax.com...

Young (and old) engineers interested in honing their talents are
invited to examine.........

http://www.analog-innovations.com/SED/MC1552LookAlike.pdf
...

As a first exercise calculate the output DC bias point... by hand
please... solutions by simulation will be ignored.

Hmm... Well first off it looks like it has hell ass gain, and that
big line of transistors seems to be a current mirror sink of around
4.6/6000 =.77 mA per transistor.
BTW... what's IM1? What is a "Q2N3904" type?

Hmm... that's weird, Q3 has no Re... so Q2 must be real low volts..
and I for that matter...
I can get an idea of Q2's Ic 'cuz R7 will always have around 5.2V across
it... it'll be between 0 (Q3 saturated) and .6mA (Q3 cutoff). Assuming
it has that low a saturation voltage with R4 and R1...
So.. Q2 will have around oh, 3uA base current? Making for 36mV across
R2? Scratch that...
Dang gain, try going backwards maybe.. Q4, Q6 and Q9-13 (nice numbering,
BTW ) will put about 5.5mA on the output... but that doesn't matter
since Q7 is a follower, so let's say output is at 3V, then Q1's C must
be 3.6V.. R5 has 4.7mA, and its emitter will be .35V, so Q3's C must be
around 1V.

But all of that can't possibly matter because it has to be set by some-
thing simple and feedback-ey like a volt divider including R2 and R9...
Well... if output drops volts by much, Q6 can't maintain a constant
current and becomes saturated... so volts across R9 drops off. Basically,
that should maintain the output above about .6 + (R9 at CCS.. .00077*3000
= 2.3V) or pretty near 3V.

So.. um... do I get a prize or anything? Or at least an "attaboy" for all
this damned thinking and typing..

Tim

--
"That's for the courts to decide." - Homer Simpson
Website @ http://webpages.charter.net/dawill/tmoranwms

 

[Jim Thompson]

On Fri, 2 Jan 2004 17:44:09 -0600, "Tim Williams"
<tmoranwms@charter.net> wrote:

"Jim Thompson" <invalid@invalid.invalid> wrote in message
news:u889vv0jpmh7tv14oqjvsataucv6g56fok@4ax.com...
Young (and old) engineers interested in honing their talents are
invited to examine.........

http://www.analog-innovations.com/SED/MC1552LookAlike.pdf
..

As a first exercise calculate the output DC bias point... by hand
please... solutions by simulation will be ignored.

Hmm... Well first off it looks like it has hell ass gain, and that
big line of transistors seems to be a current mirror sink of around
4.6/6000 =.77 mA per transistor.
BTW... what's IM1?

Im1 is an *ammeter*... just another of my many gimmicks I use in
PSpice.

What is a "Q2N3904" type?

It's just the model name for a 2N3904 transistor.

Hmm... that's weird, Q3 has no Re... so Q2 must be real low volts..
and I for that matter...
I can get an idea of Q2's Ic 'cuz R7 will always have around 5.2V across
it... it'll be between 0 (Q3 saturated) and .6mA (Q3 cutoff). Assuming
it has that low a saturation voltage with R4 and R1...
So.. Q2 will have around oh, 3uA base current? Making for 36mV across
R2? Scratch that...
Dang gain, try going backwards maybe.. Q4, Q6 and Q9-13 (nice numbering,
BTW ) will put about 5.5mA on the output... but that doesn't matter
since Q7 is a follower, so let's say output is at 3V, then Q1's C must
be 3.6V.. R5 has 4.7mA, and its emitter will be .35V, so Q3's C must be
around 1V.

But all of that can't possibly matter because it has to be set by some-
thing simple and feedback-ey like a volt divider including R2 and R9...
Well... if output drops volts by much, Q6 can't maintain a constant
current and becomes saturated... so volts across R9 drops off. Basically,
that should maintain the output above about .6 + (R9 at CCS.. .00077*3000
= 2.3V) or pretty near 3V.

So.. um... do I get a prize or anything? Or at least an "attaboy" for all
this damned thinking and typing..

Tim

*Attaboy* for trying ;-)

The real winners will come out of this *understanding* why it works.

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

 

[Genome]

"Jim Thompson" <invalid@invalid.invalid> wrote in message
news:u889vv0jpmh7tv14oqjvsataucv6g56fok@4ax.com...

Young (and old) engineers interested in honing their talents are
invited to examine.........

http://www.analog-innovations.com/SED/MC1552LookAlike.pdf

which is a workup of my old MC1552 design (from the '60's) but using
discrete transistors.

As a first exercise calculate the output DC bias point... by hand
please... solutions by simulation will be ignored.

If you think that is harsh, keep in mind that I did this design when I
was around 25 years old, and did ALL the design work on a pad of
paper.

(We'll attack the AC analysis later.)

Enjoy!

(If I have the time I will try to keep you exercised (or is it
exorcised ? about every week or so.)

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

Howzabout......

Q8 and Q5 drop 1.2V so current is (6 - 1.2)/6K or 800uA.

800uA in R9 is 2.4V.

Add 0.6V for Q2 Vbe and

The output sits at 3V

DNA

 

[Genome]

"Genome" <genome@nothere.com> wrote in message
news:%vuJb.16$kX1.13@newsfep1-gui.server.ntli.net...

"Jim Thompson" <invalid@invalid.invalid> wrote in message
news:u889vv0jpmh7tv14oqjvsataucv6g56fok@4ax.com...
Young (and old) engineers interested in honing their talents are
invited to examine.........

http://www.analog-innovations.com/SED/MC1552LookAlike.pdf

which is a workup of my old MC1552 design (from the '60's) but using
discrete transistors.

As a first exercise calculate the output DC bias point... by hand
please... solutions by simulation will be ignored.

If you think that is harsh, keep in mind that I did this design when I
was around 25 years old, and did ALL the design work on a pad of
paper.

(We'll attack the AC analysis later.)

Enjoy!

(If I have the time I will try to keep you exercised (or is it
exorcised ? about every week or so.)

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

Howzabout......

Q8 and Q5 drop 1.2V so current is (6 - 1.2)/6K or 800uA.

800uA in R9 is 2.4V.

Add 0.6V for Q2 Vbe and

The output sits at 3V

DNA

Oh.... and the Tempco. Q8 and Q5 do 2 lots of varying across 2 lots of 3K
which becomes 1 lot of varying in the 1 lot of 3K, R9.... which cancels the
one lot of varying in Q2. So the Tempco is sort of zero.

DNA

 

[Fred Bloggs]

Genome wrote:

"Genome" <genome@nothere.com> wrote in message
news:%vuJb.16$kX1.13@newsfep1-gui.server.ntli.net...

"Jim Thompson" <invalid@invalid.invalid> wrote in message
news:u889vv0jpmh7tv14oqjvsataucv6g56fok@4ax.com...

Young (and old) engineers interested in honing their talents are
invited to examine.........

http://www.analog-innovations.com/SED/MC1552LookAlike.pdf

which is a workup of my old MC1552 design (from the '60's) but using
discrete transistors.

As a first exercise calculate the output DC bias point... by hand
please... solutions by simulation will be ignored.

If you think that is harsh, keep in mind that I did this design when I
was around 25 years old, and did ALL the design work on a pad of
paper.

(We'll attack the AC analysis later.)

Enjoy!

(If I have the time I will try to keep you exercised (or is it
exorcised ? about every week or so.)

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

Howzabout......

Q8 and Q5 drop 1.2V so current is (6 - 1.2)/6K or 800uA.

800uA in R9 is 2.4V.

Add 0.6V for Q2 Vbe and

The output sits at 3V

DNA




Oh.... and the Tempco. Q8 and Q5 do 2 lots of varying across 2 lots of 3K
which becomes 1 lot of varying in the 1 lot of 3K, R9.... which cancels the
one lot of varying in Q2. So the Tempco is sort of zero.

DNA

What is the Q1 Ic bias point stabilization factor against each
transistor beta variation?

 

[Genome]

"Fred Bloggs" <nospam@nospam.com> wrote in message
news:3FF6F6D0.6040907@nospam.com...

Genome wrote:
"Genome" <genome@nothere.com> wrote in message
news:%vuJb.16$kX1.13@newsfep1-gui.server.ntli.net...

"Jim Thompson" <invalid@invalid.invalid> wrote in message
news:u889vv0jpmh7tv14oqjvsataucv6g56fok@4ax.com...

Young (and old) engineers interested in honing their talents are
invited to examine.........

http://www.analog-innovations.com/SED/MC1552LookAlike.pdf

which is a workup of my old MC1552 design (from the '60's) but using
discrete transistors.

As a first exercise calculate the output DC bias point... by hand
please... solutions by simulation will be ignored.

If you think that is harsh, keep in mind that I did this design when I
was around 25 years old, and did ALL the design work on a pad of
paper.

(We'll attack the AC analysis later.)

Enjoy!

(If I have the time I will try to keep you exercised (or is it
exorcised ? about every week or so.)

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

Howzabout......

Q8 and Q5 drop 1.2V so current is (6 - 1.2)/6K or 800uA.

800uA in R9 is 2.4V.

Add 0.6V for Q2 Vbe and

The output sits at 3V

DNA




Oh.... and the Tempco. Q8 and Q5 do 2 lots of varying across 2 lots of
3K
which becomes 1 lot of varying in the 1 lot of 3K, R9.... which cancels
the
one lot of varying in Q2. So the Tempco is sort of zero.

DNA



What is the Q1 Ic bias point stabilization factor against each
transistor beta variation?

I haven't got a minimal idea of any concept of a basic clue.

Hey, I failed the employment question before the Fields filled me in. Plus a
few other clues. Cute, and no denying it. It's a state of mind.

Jim Thompson... the Teacher. There's a new concept, gotta go down Burger
King...

Later


DNA

 

[Spehro Pefhany]

On Thu, 01 Jan 2004 15:45:48 -0700, the renowned Jim Thompson
<invalid@invalid.invalid> wrote:

Young (and old) engineers interested in honing their talents are
invited to examine.........

http://www.analog-innovations.com/SED/MC1552LookAlike.pdf

which is a workup of my old MC1552 design (from the '60's) but using
discrete transistors.

As a first exercise calculate the output DC bias point... by hand
please... solutions by simulation will be ignored.

If you think that is harsh, keep in mind that I did this design when I
was around 25 years old, and did ALL the design work on a pad of
paper.

Bias curent is set by R8+R10 and 6V-Vb*2 or 0.77mA.

Q4..Q13 will thus sink 4.6mA if not saturated.
Q6 shifts the voltage at the output by -2.31V.

Turning to the input, just estimate the rather low
voltage across R4 for the moment.. since the voltage at
the base of Q3 will be 0.7 for linear operation, the
collector current for Q2 is 0.58mA, and the emitter
voltage due to that will be around 45mV.

meaning the base of Q2 must be around 0.75V. Voltage at
E of Q7 will be 3.06V, voltage at base of Q7 will be
3.76V. Emitter current 4.4mA, so voltage across R3 is
about 0.33V.

Tempco of output voltage- first order the Vbe changes
(and tempco of R10/R8/R9 cancel out, but Q7 is operating
at 6 times the current of Q8/Q6, so there will be a diff.
between the Vbe tempcos of Vt/T * ln(Ic2/Ic1)
= 149uV/K @ 27°C, which is also the tempco of the output
voltage, in the +ve direction.

Jim: I'll send an empty followup to this message (to abse only) with a
simple & unrelated schematic attached. Comments on it?


Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
speff@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com

 

[Jim Thompson]

On Sun, 04 Jan 2004 17:27:03 GMT, Spehro Pefhany
<speffSNIP@interlogDOTyou.knowwhat> wrote:

On Thu, 01 Jan 2004 15:45:48 -0700, the renowned Jim Thompson
invalid@invalid.invalid> wrote:

Young (and old) engineers interested in honing their talents are
invited to examine.........

http://www.analog-innovations.com/SED/MC1552LookAlike.pdf

which is a workup of my old MC1552 design (from the '60's) but using
discrete transistors.

As a first exercise calculate the output DC bias point... by hand
please... solutions by simulation will be ignored.

If you think that is harsh, keep in mind that I did this design when I
was around 25 years old, and did ALL the design work on a pad of
paper.

Bias curent is set by R8+R10 and 6V-Vb*2 or 0.77mA.

Q4..Q13 will thus sink 4.6mA if not saturated.
Q6 shifts the voltage at the output by -2.31V.

Turning to the input, just estimate the rather low
voltage across R4 for the moment.. since the voltage at
the base of Q3 will be 0.7 for linear operation, the
collector current for Q2 is 0.58mA, and the emitter
voltage due to that will be around 45mV.

meaning the base of Q2 must be around 0.75V. Voltage at
E of Q7 will be 3.06V, voltage at base of Q7 will be
3.76V. Emitter current 4.4mA, so voltage across R3 is
about 0.33V.

Tempco of output voltage- first order the Vbe changes
(and tempco of R10/R8/R9 cancel out, but Q7 is operating
at 6 times the current of Q8/Q6, so there will be a diff.
between the Vbe tempcos of Vt/T * ln(Ic2/Ic1)
= 149uV/K @ 27°C, which is also the tempco of the output
voltage, in the +ve direction.

At *constant* current *all* transistors have the *same* TC
irrespective of current (unless in current crowding in low current
"leaky" conditions).

The *tracking* problems occur because the *current* changes due to
other influences... like the bias.

Jim: I'll send an empty followup to this message (to abse only) with a
simple & unrelated schematic attached. Comments on it?


Best regards,
Spehro Pefhany

I'll watch for it.

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

 

[Spehro Pefhany]

On Sun, 04 Jan 2004 10:34:53 -0700, the renowned Jim Thompson
<invalid@invalid.invalid> wrote:

At *constant* current *all* transistors have the *same* TC
irrespective of current (unless in current crowding in low current
"leaky" conditions).

Mmm.. but the *difference* between dVbe/dT in two identical
transistors running at different currents is non-zero isn't it?
I could have sworn I used that effect to advantage, using some
accurate models you kindly pointed me to about a year ago.

The *tracking* problems occur because the *current* changes due to
other influences... like the bias.

I'll look at it again a bit later.

Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
speff@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com

 

[Fred Bloggs]

Spehro Pefhany wrote:

On Sun, 04 Jan 2004 10:34:53 -0700, the renowned Jim Thompson
invalid@invalid.invalid> wrote:


At *constant* current *all* transistors have the *same* TC
irrespective of current (unless in current crowding in low current
"leaky" conditions).


Mmm.. but the *difference* between dVbe/dT in two identical
transistors running at different currents is non-zero isn't it?
I could have sworn I used that effect to advantage, using some
accurate models you kindly pointed me to about a year ago.

Yep- about 200uV/oC for each factor 10x current. But you might note that
the level shifting current is approximately the same as Q2 current, so
the Vbe's in the cancellation equation are negligibly the same.

The *tracking* problems occur because the *current* changes due to
other influences... like the bias.


I'll look at it again a bit later.

Best regards,
Spehro Pefhany

 

[Spehro Pefhany]

On Sun, 04 Jan 2004 17:53:36 GMT, the renowned Fred Bloggs
<nospam@nospam.com> wrote:

Yep- about 200uV/oC for each factor 10x current. But you might note that
the level shifting current is approximately the same as Q2 current, so
the Vbe's in the cancellation equation are negligibly the same.

Yes okay, it's outside the DC FB loop..

Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
speff@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com