Design Compiler: Output mux for testing fails timing.

Hi,

Would someone look at the simplified code below and help me set the
timing constraints?


CODE:

output dataOut;
input clkIn;
input dataIn;
input TEST;

// Module which divides the clock by two
clkdiv clkdiv_inst (
.in(clkIn),
.out(clkIn_div_2).
);


// Latch data into two registers
always @ (posedge clkIn) begin
data_reg1 <= dataIn;
data_reg2 < = data_reg2;
end

// Output data at half the rate
always @ (posedge clkIn_div_2) begin
dataOut_reg <= {data_reg1, data_reg2};


// Mux between half rate and full rate
assign dataOut = (TEST) ? dataIn : dataOut_reg;




DESCRIPTION:
I latch in the data into two registers and output it at half the rate.
In test mode (TEST) I bypass the division by two and send the data
right out as is.


PROBLEM:
The data rate is very high (>1GHz) and I fail timig when in test mode.
HOWEVER in test mode I will be clocking my circuit a lot slower, so
this isn't an issue.


WHAT I WANT:
Tell design compiler to ignore the case when TEST==1.

 

[michaelst@gmail.com]

Probably following command will help you:
set_case_analysis 0 TEST

rafeng@rogers.com wrote:

Hi,

Would someone look at the simplified code below and help me set the
timing constraints?


CODE:

output dataOut;
input clkIn;
input dataIn;
input TEST;

// Module which divides the clock by two
clkdiv clkdiv_inst (
.in(clkIn),
.out(clkIn_div_2).
);


// Latch data into two registers
always @ (posedge clkIn) begin
data_reg1 <= dataIn;
data_reg2 < = data_reg2;
end

// Output data at half the rate
always @ (posedge clkIn_div_2) begin
dataOut_reg <= {data_reg1, data_reg2};


// Mux between half rate and full rate
assign dataOut = (TEST) ? dataIn : dataOut_reg;




DESCRIPTION:
I latch in the data into two registers and output it at half the rate.
In test mode (TEST) I bypass the division by two and send the data
right out as is.


PROBLEM:
The data rate is very high (>1GHz) and I fail timig when in test mode.
HOWEVER in test mode I will be clocking my circuit a lot slower, so
this isn't an issue.


WHAT I WANT:
Tell design compiler to ignore the case when TEST==1.

 

good question


any positive suggestion is welcome
goodness to you all

michaelst@gmail.com 寫道：

Probably following command will help you:
set_case_analysis 0 TEST

rafeng@rogers.com wrote:
Hi,

Would someone look at the simplified code below and help me set the
timing constraints?


CODE:

output dataOut;
input clkIn;
input dataIn;
input TEST;

// Module which divides the clock by two
clkdiv clkdiv_inst (
.in(clkIn),
.out(clkIn_div_2).
);


// Latch data into two registers
always @ (posedge clkIn) begin
data_reg1 <= dataIn;
data_reg2 < = data_reg2;
end

// Output data at half the rate
always @ (posedge clkIn_div_2) begin
dataOut_reg <= {data_reg1, data_reg2};


// Mux between half rate and full rate
assign dataOut = (TEST) ? dataIn : dataOut_reg;




DESCRIPTION:
I latch in the data into two registers and output it at half the rate.
In test mode (TEST) I bypass the division by two and send the data
right out as is.


PROBLEM:
The data rate is very high (>1GHz) and I fail timig when in test mode.
HOWEVER in test mode I will be clocking my circuit a lot slower, so
this isn't an issue.


WHAT I WANT:
Tell design compiler to ignore the case when TEST==1.

 

Probably following command will help you:
set_case_analysis 0 TEST

EXACLY what I was looking for! This will help me a lot, Thanks!

 

michaelst@gmail.com wrote:

Probably following command will help you:
set_case_analysis 0 TEST

One more question: Can I set constraints for both cases using this
set_case_analysis or a varient of it? For example if TEST==0 then clkIn
= 1GHz, if TEST==1 then clkIn = 1MHz and put that in the syntheis
constraints?