Design chaos

S

sridar

Guest
Hi all,

I am working on a design, where there are n modules. Each module i
connected with next module in sequential fashion.

like, data generator -> encoder 1 -> encoder 2-> modulator -> demodulator
-> decoder2 -> decoder1

The output of decoder1 should be same as data generator. I have tested eac
module in FPGA and also the following configurations


data generator -> encoder 1 -> encoder 2-> decoder2 ->decoder1
----------Works fine

data generator -> encoder 2 -> modulator -> demodulator -> decoder2
----------Works fine


But, when I integrate the all the modules, the design is not working a
expected. I need to reset the board for 5,6 times for the output to com
correctly. The timing analyzer reported no error.

BTW, I designed all the modules using VHDL in ISE 12.3 and tried in tw
hardware boards 1. Spartan-6 sp601 kit 2. Spartan-3 based baord



---------------------------------------
Posted through http://www.FPGARelated.com
 
On Nov 12, 7:54 am, "sridar" <srisridar@n_o_s_p_a_m.gmail.com> wrote:
Hi all,

I am working on a design, where there are n modules. Each module is
connected with next module in sequential fashion.

like, data generator -> encoder 1 -> encoder 2-> modulator -> demodulator
-> decoder2 -> decoder1

The output of decoder1 should be same as data generator. I have tested each
module in FPGA and also the following configurations

data generator -> encoder 1 -> encoder 2-> decoder2 ->decoder1
----------Works fine

data generator -> encoder 2 -> modulator -> demodulator -> decoder2
----------Works fine

But, when I integrate the all the modules, the design is not working as
expected. I need to reset the board for 5,6 times for the output to come
correctly. The timing analyzer reported no error.

BTW, I designed all the modules using VHDL in ISE 12.3 and tried in two
hardware boards 1. Spartan-6 sp601 kit 2. Spartan-3 based baord
Click to expand...
First question, did you simulate the design? I find it much easier to
view internals in simulation than on a chip.

Second, try monitoring each of the points in the upstream side with a
separate downstream chain...

gen->encode1-+->encode2-+->mod->demod->decode2->decode1->monitor
| |
| +->decode2->decode1->monitor
|
+->decode1->monitor

This may at least point to what is failing.

It is possible you have some issues with your clocking. Perhaps you
can describe how you perform that. I would expect the encode and
modulate processes create multiple samples for each sample input. Are
you using a high speed clock and enabling each section as
appropriate?

Rick
 
Do your modules operate using different clocks? If so you may have
clock boundary crossing problems.

John Adair
Enterpoint Ltd. - Home of Drigmorn3. The Spartan-6 Development Board.


On Nov 12, 12:54 pm, "sridar" <srisridar@n_o_s_p_a_m.gmail.com> wrote:
Hi all,

I am working on a design, where there are n modules. Each module is
connected with next module in sequential fashion.

like,  data generator -> encoder 1 -> encoder 2-> modulator -> demodulator
-> decoder2 -> decoder1

The output of decoder1 should be same as data generator. I have tested each
module in FPGA  and also the following configurations

data generator -> encoder 1 -> encoder 2->  decoder2 ->decoder1            
  ----------Works fine

data generator -> encoder 2 ->  modulator -> demodulator  -> decoder2      
 ----------Works fine

But, when I integrate the all the modules, the design is not working as
expected. I need to reset the board for 5,6 times for the output to come
correctly. The timing analyzer reported no error.

BTW, I designed all the modules using VHDL in ISE 12.3 and tried in two
hardware boards 1. Spartan-6 sp601 kit  2. Spartan-3 based baord

---------------------------------------        
Posted throughhttp://www.FPGARelated.com
Click to expand...
 
On Nov 12, 7:54 am, "sridar" <srisridar@n_o_s_p_a_m.gmail.com> wrote:
Hi all,

I am working on a design, where there are n modules. Each module is
connected with next module in sequential fashion.

like,  data generator -> encoder 1 -> encoder 2-> modulator -> demodulator
-> decoder2 -> decoder1

The output of decoder1 should be same as data generator. I have tested each
module in FPGA  and also the following configurations

data generator -> encoder 1 -> encoder 2->  decoder2 ->decoder1            
  ----------Works fine

data generator -> encoder 2 ->  modulator -> demodulator  -> decoder2      
 ----------Works fine

But, when I integrate the all the modules, the design is not working as
expected. I need to reset the board for 5,6 times for the output to come
correctly. The timing analyzer reported no error.

BTW, I designed all the modules using VHDL in ISE 12.3 and tried in two
hardware boards 1. Spartan-6 sp601 kit  2. Spartan-3 based baord

---------------------------------------        
Posted throughhttp://www.FPGARelated.com
How about an occasional bit error between the modulator and
Click to expand...
demodulator causes the decoder1 to get lost where as decoder2 is more
robust.
 
Hey all,

It was basic mistake. Even though, modulator was working fine, this bloc
introduces some additional bits at the start, which I couldn't observe i
Hardware. So it made the decoder to interpret the data in different way
Now I could solve it. thanks all for the reply

On Nov 12, 7:54=A0am, "sridar" <srisridar@n_o_s_p_a_m.gmail.com> wrote:
Hi all,

I am working on a design, where there are n modules. Each module is
connected with next module in sequential fashion.

like, =A0data generator -> encoder 1 -> encoder 2-> modulator -
demodula=
tor
-> decoder2 -> decoder1

The output of decoder1 should be same as data generator. I have teste
ea=
ch
module in FPGA =A0and also the following configurations

data generator -> encoder 1 -> encoder 2-> =A0decoder2 ->decoder1 =A
=A0=
=A0 =A0 =A0 =A0
=A0 ----------Works fine

data generator -> encoder 2 -> =A0modulator -> demodulator =A0-
decoder2=
=A0 =A0 =A0
=A0----------Works fine

But, when I integrate the all the modules, the design is not working as
expected. I need to reset the board for 5,6 times for the output t
come
correctly. The timing analyzer reported no error.

BTW, I designed all the modules using VHDL in ISE 12.3 and tried in two
hardware boards 1. Spartan-6 sp601 kit =A02. Spartan-3 based baord

--------------------------------------- =A0 =A0 =A0 =A0
Posted throughhttp://www.FPGARelated.com
How about an occasional bit error between the modulator and
demodulator causes the decoder1 to get lost where as decoder2 is more
robust.
Click to expand...
---------------------------------------
Posted through http://www.FPGARelated.com
 
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