Desiging a synchronous divide by 3 circuit in verilog

J

jacky

Guest
I have designed a syhnchronous divide by 3 sequential circuit with 2 D
flip flops

I have written this verilog code :

module sync_counter(
output reg q2;
input clk,rst_n);
reg d1,q,d2;

always @(q1) begin
d1 = q2;
d2 = ~(q1 | q2);
end

always @(posedge clk or negedge rst_n)
begin
if (rst_n)
q2 <= 0;
q1 <= 0;
end

else begin
q2<=d2;
q1 <= d1;
end
endmodule

I guess combinational block i have implemented is wrong. Can anyone
help

--Jacky
 
jacky wrote:
I have designed a syhnchronous divide by 3 sequential circuit with 2 D
flip flops

I have written this verilog code :

module sync_counter(
output reg q2;
input clk,rst_n);
reg d1,q,d2;

always @(q1) begin
d1 = q2;
d2 = ~(q1 | q2);
end

always @(posedge clk or negedge rst_n)
begin
if (rst_n)
q2 <= 0;
q1 <= 0;
end

else begin
q2<=d2;
q1 <= d1;
end
endmodule

I guess combinational block i have implemented is wrong. Can anyone
help

--Jacky
Click to expand...

So, tell me: what does your circuit do when q2 changes but q1 stays the
same?

q1 q2 | d1 d2
------+------
x x | x x
reset
0 0 | 0 1
0 1 | ? ?
 
On Jun 2, 8:32 pm, John_H <newsgr...@johnhandwork.com> wrote:
jacky wrote:
I have designed a syhnchronous divide by 3 sequential circuit with 2 D
flip flops

I have written this verilog code :

module sync_counter(
output reg q2;
input clk,rst_n);
reg d1,q,d2;

always @(q1) begin
d1 = q2;
d2 = ~(q1 | q2);
end

always @(posedge clk or negedge rst_n)
begin
if (rst_n)
q2 <= 0;
q1 <= 0;
end

else begin
q2<=d2;
q1 <= d1;
end
endmodule

I guess combinational block i have implemented is wrong. Can anyone
help

--Jacky

So, tell me: what does your circuit do when q2 changes but q1 stays the
same?

q1 q2 | d1 d2
------+------
x x | x x
reset
0 0 | 0 1
0 1 | ? ?- Hide quoted text -

- Show quoted text -
Click to expand...
To my understanding, with the available outputs as q2 = 1 and q1 same
as previous state , inputs d1 = 1 and d2 = 0.

--Jacky
 
jacky_mrini@hotmail.com wrote:
On Jun 2, 8:32 pm, John_H <newsgr...@johnhandwork.com> wrote:
jacky wrote:
I have designed a syhnchronous divide by 3 sequential circuit with 2 D
flip flops
I have written this verilog code :
module sync_counter(
output reg q2;
input clk,rst_n);
reg d1,q,d2;
always @(q1) begin
d1 = q2;
d2 = ~(q1 | q2);
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n)
q2 <= 0;
q1 <= 0;
end
else begin
q2<=d2;
q1 <= d1;
end
endmodule
I guess combinational block i have implemented is wrong. Can anyone
help
--Jacky
So, tell me: what does your circuit do when q2 changes but q1 stays the
same?

q1 q2 | d1 d2
------+------
x x | x x
reset
0 0 | 0 1
0 1 | ? ?- Hide quoted text -

- Show quoted text -

To my understanding, with the available outputs as q2 = 1 and q1 same
as previous state , inputs d1 = 1 and d2 = 0.

--Jacky
Click to expand...
If your logic for the d values was actually combinatorial, you'd be
correct. Your always block doesn't provide a continuous assignment.

Ask yourself why
assign d1 = q2;
and
assign d2 = ~(q1 | q2);
give you the results that you want yet
always @(q1) begin
d1 = q2;
d2 = ~(q1 | q2);
end
doesn't.

Think of the problem in the way a simulator schedules events.
 
Hi
This circuit will generate divide by 3 clk with 33.3 and 66.6 %duty
cycle taking q1, a2 as otputs
to get 50% duty cycle
u need to use a neg edge vlk to drive a third flop whose input is q2
and then or the final output of this gate with q2
u will get 50%duty cycle

On Jun 2, 4:41 am, jacky <kaul.v...@hotmail.com> wrote:
I have designed a syhnchronous divide by 3 sequential circuit with 2 D
flip flops

I have written this verilog code :

module sync_counter(
output reg q2;
input clk,rst_n);
reg d1,q,d2;

always @(q1) begin
d1 = q2;
d2 = ~(q1 | q2);
end

always @(posedge clk or negedge rst_n)
begin
if (rst_n)
q2 <= 0;
q1 <= 0;
end

else begin
q2<=d2;
q1 <= d1;
end
endmodule

I guess combinational block i have implemented is wrong. Can anyone
help

--Jacky
Click to expand...
 
Since you're not the original poster and you're trying to help: did you
simulate this design that was submitted over a month ago? The specific
issue from the original poster was a problem with the combinatorial block
where d1 and d2 get assigned. By inspection, one can see that d1 and d2
only change when q1 changes though the intent of the combinatorial block
would be to change the values for changes to q1 OR q2 for the divide-by-3.

The circuit does not provide a divide-by-3 as coded. There's no 33% or 66%
duty cycle because the circuit stalls.


<srisai2k3@gmail.com> wrote in message
news:1183981212.837830.98100@e16g2000pri.googlegroups.com...
Hi
This circuit will generate divide by 3 clk with 33.3 and 66.6 %duty
cycle taking q1, a2 as otputs
to get 50% duty cycle
u need to use a neg edge vlk to drive a third flop whose input is q2
and then or the final output of this gate with q2
u will get 50%duty cycle

On Jun 2, 4:41 am, jacky <kaul.v...@hotmail.com> wrote:
I have designed a syhnchronous divide by 3 sequential circuit with 2 D
flip flops

I have written this verilog code :

module sync_counter(
output reg q2;
input clk,rst_n);
reg d1,q,d2;

always @(q1) begin
d1 = q2;
d2 = ~(q1 | q2);
end

always @(posedge clk or negedge rst_n)
begin
if (rst_n)
q2 <= 0;
q1 <= 0;
end

else begin
q2<=d2;
q1 <= d1;
end
endmodule

I guess combinational block i have implemented is wrong. Can anyone
help

--Jacky
Click to expand...
 
srisai2k3@gmail.com wrote:

This circuit will generate divide by 3 clk with 33.3 and 66.6 %duty
cycle taking q1, a2 as otputs to get 50% duty cycle
u need to use a neg edge vlk to drive a third flop whose input is q2
and then or the final output of this gate with q2
u will get 50%duty cycle
Click to expand...
With the assumption of 50% on the input clock.

-- glen
 
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