Desgining 4Bits ALU

T

Tadeu

Guest
Hi I am working in a university project trying to build a 4Bits ALU I
am havaing problems with this:
/***************************************/
module Logic(a, b, s, f);
input [0:3] a,b;
input [0:1] s;
output [0:3] f;
case(s)
2'b00 : begin//AND
assign f[0] = a[0] & b[0];
assign f[1] = a[1] & b[1];
assign f[2] = a[2] & b[2];
assign f[3] = a[3] & b[3];
end
2'b01 : begin//OR
assign f[0] = a[0] | b[0];
assign f[1] = a[1] | b[1];
assign f[2] = a[2] | b[2];
assign f[3] = a[3] | b[3];
end
default: begin
end
endcase
endmodule
/***************************************/
verilog always return:
///////////////
and.v:99: parse error
and.v:101: error: invalid module item. Did you forget an initial or
always?
and.v:105: parse error
and.v:107: error: invalid module item. Did you forget an initial or
always?
and.v:111: parse error
and.v:120: error: invalid module item. Did you forget an initial or
always?
/////////////
where line 99 is the "case(s)"

Any sugestions?
 
Tadeu wrote:
Hi I am working in a university project trying to build a 4Bits ALU I
am havaing problems with this:
/***************************************/
module Logic(a, b, s, f);
input [0:3] a,b;
input [0:1] s;
output [0:3] f;
case(s)
2'b00 : begin//AND
assign f[0] = a[0] & b[0];
assign f[1] = a[1] & b[1];
assign f[2] = a[2] & b[2];
assign f[3] = a[3] & b[3];
end
2'b01 : begin//OR
assign f[0] = a[0] | b[0];
assign f[1] = a[1] | b[1];
assign f[2] = a[2] | b[2];
assign f[3] = a[3] | b[3];
end
default: begin
end
endcase
endmodule
/***************************************/
verilog always return:
///////////////
and.v:99: parse error
and.v:101: error: invalid module item. Did you forget an initial or
always?
and.v:105: parse error
and.v:107: error: invalid module item. Did you forget an initial or
always?
and.v:111: parse error
and.v:120: error: invalid module item. Did you forget an initial or
always?
/////////////
where line 99 is the "case(s)"

Any sugestions?
Click to expand...
The case() is not valid without an encompassing initial or always block.
I remember when I first started Verilog, I wanted to do an "assign"
with an if/else block. Can't do that either.

If you want the results of the case to be combinatorial and you're using
Verilog2001 constructs, add an always@* before your case() and you're
good to go.

If you check your Verilog textbook, you should find reference to what
constructs must be used inside a sequential block.
 
John_H escreveu:

Tadeu wrote:
Hi I am working in a university project trying to build a 4Bits ALU I
am havaing problems with this:
/***************************************/
module Logic(a, b, s, f);
input [0:3] a,b;
input [0:1] s;
output [0:3] f;
case(s)
2'b00 : begin//AND
assign f[0] = a[0] & b[0];
assign f[1] = a[1] & b[1];
assign f[2] = a[2] & b[2];
assign f[3] = a[3] & b[3];
end
2'b01 : begin//OR
assign f[0] = a[0] | b[0];
assign f[1] = a[1] | b[1];
assign f[2] = a[2] | b[2];
assign f[3] = a[3] | b[3];
end
default: begin
end
endcase
endmodule
/***************************************/
verilog always return:
///////////////
and.v:99: parse error
and.v:101: error: invalid module item. Did you forget an initial or
always?
and.v:105: parse error
and.v:107: error: invalid module item. Did you forget an initial or
always?
and.v:111: parse error
and.v:120: error: invalid module item. Did you forget an initial or
always?
/////////////
where line 99 is the "case(s)"

Any sugestions?

The case() is not valid without an encompassing initial or always block.
I remember when I first started Verilog, I wanted to do an "assign"
with an if/else block. Can't do that either.

If you want the results of the case to be combinatorial and you're using
Verilog2001 constructs, add an always@* before your case() and you're
good to go.

If you check your Verilog textbook, you should find reference to what
constructs must be used inside a sequential block.
Click to expand...
So what should I do to achieve this behavior do something depending on
the entry of a 4bits data? The only way is to create it manually using
ands and or an not logical doors?
 
Tadeu wrote:
John_H escreveu:

Tadeu wrote:
Hi I am working in a university project trying to build a 4Bits ALU I
am havaing problems with this:
/***************************************/
module Logic(a, b, s, f);
input [0:3] a,b;
input [0:1] s;
output [0:3] f;
case(s)
2'b00 : begin//AND
assign f[0] = a[0] & b[0];
assign f[1] = a[1] & b[1];
assign f[2] = a[2] & b[2];
assign f[3] = a[3] & b[3];
end
2'b01 : begin//OR
assign f[0] = a[0] | b[0];
assign f[1] = a[1] | b[1];
assign f[2] = a[2] | b[2];
assign f[3] = a[3] | b[3];
end
default: begin
end
endcase
endmodule
/***************************************/
verilog always return:
///////////////
and.v:99: parse error
and.v:101: error: invalid module item. Did you forget an initial or
always?
and.v:105: parse error
and.v:107: error: invalid module item. Did you forget an initial or
always?
and.v:111: parse error
and.v:120: error: invalid module item. Did you forget an initial or
always?
/////////////
where line 99 is the "case(s)"

Any sugestions?
The case() is not valid without an encompassing initial or always block.
I remember when I first started Verilog, I wanted to do an "assign"
with an if/else block. Can't do that either.

If you want the results of the case to be combinatorial and you're using
Verilog2001 constructs, add an always@* before your case() and you're
good to go.

If you check your Verilog textbook, you should find reference to what
constructs must be used inside a sequential block.

So what should I do to achieve this behavior do something depending on
the entry of a 4bits data? The only way is to create it manually using
ands and or an not logical doors?
Click to expand...
I repeat myself:

If you want the results of the case to be combinatorial and you're using
Verilog2001 constructs, add an always@* before your case() and you're
good to go.
_____

Personally I'd use the conditional operator ( a ? b : c ) in an assign
either cascaded or in a wide OR.
 
John_H wrote:
Tadeu wrote:
John_H escreveu:

Tadeu wrote:
Hi I am working in a university project trying to build a 4Bits ALU I
am havaing problems with this:
/***************************************/
module Logic(a, b, s, f);
input [0:3] a,b;
input [0:1] s;
output [0:3] f;
case(s)
2'b00 : begin//AND
assign f[0] = a[0] & b[0];
assign f[1] = a[1] & b[1];
assign f[2] = a[2] & b[2];
assign f[3] = a[3] & b[3];
end
2'b01 : begin//OR
assign f[0] = a[0] | b[0];
assign f[1] = a[1] | b[1];
assign f[2] = a[2] | b[2];
assign f[3] = a[3] | b[3];
end
default: begin
end
endcase
endmodule
/***************************************/
verilog always return:
///////////////
and.v:99: parse error
and.v:101: error: invalid module item. Did you forget an initial or
always?
and.v:105: parse error
and.v:107: error: invalid module item. Did you forget an initial or
always?
and.v:111: parse error
and.v:120: error: invalid module item. Did you forget an initial or
always?
/////////////
where line 99 is the "case(s)"

Any sugestions?
The case() is not valid without an encompassing initial or always block.
I remember when I first started Verilog, I wanted to do an "assign"
with an if/else block. Can't do that either.

If you want the results of the case to be combinatorial and you're using
Verilog2001 constructs, add an always@* before your case() and you're
good to go.

If you check your Verilog textbook, you should find reference to what
constructs must be used inside a sequential block.

So what should I do to achieve this behavior do something depending on
the entry of a 4bits data? The only way is to create it manually using
ands and or an not logical doors?

I repeat myself:

If you want the results of the case to be combinatorial and you're using
Verilog2001 constructs, add an always@* before your case() and you're
good to go.
_____

Personally I'd use the conditional operator ( a ? b : c ) in an assign
either cascaded or in a wide OR.
Click to expand...
Well, almost good to go...
You still need to get rid of the "assign" in each line within the
always
block and you need to realize that you are describing a latch by not
assigning anything to f in the default case. Is this what you really
want? By the way bitwise AND and OR operators do not require you
to write an assignment for each bit.

assign f[0] = a[0] & b[0];
assign f[1] = a[1] & b[1];
assign f[2] = a[2] & b[2];
assign f[3] = a[3] & b[3];

is equivalent to:

assign f = a & b;

HTH,
Gabor
 
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