Derived Clock

[Triste]

Hi,

To derive a slow clock, say 1 Hz from 50 MHz or 32.768 KHz, does
anyone know the difference between using cascaded divide-by-2 counters
and using a single long divider?

Thanks very much in advance.

 

[Just an Illusion]

Hi Triste,

You have certainly some other features, but one of the first is
certainly a problem of clock race.
In case of cascaded divide-by-2, your output clock signal take each time
some little transmission delay; above a certain limit the output clock
is no more synchronized with input one.
With the single long divider (based on counter I think) you can reduce
this clock slide. And it is certainly more simple to resynchronize the
out clock.

JaI

Triste wrote:

Hi,

To derive a slow clock, say 1 Hz from 50 MHz or 32.768 KHz, does
anyone know the difference between using cascaded divide-by-2 counters
and using a single long divider?

Thanks very much in advance.

 

[Just an Illusion]

Hi Triste,

Triste wrote:

Just an Illusion <illusion_to_net@yahoo.fr> wrote in message news:<40ED4764.2090900@yahoo.fr>...


Hi Triste,

You have certainly some other features, but one of the first is
certainly a problem of clock race.
In case of cascaded divide-by-2, your output clock signal take each time
some little transmission delay; above a certain limit the output clock
is no more synchronized with input one.
With the single long divider (based on counter I think) you can reduce
this clock slide. And it is certainly more simple to resynchronize the
out clock.

JaI




Hi JaI, thanks for the comments.

Actually my question is, to derive 1 Hz from 32.768 KHz, is there any
difference between using cascading D-type flip flops built with
primitive gates and using divide-by-n counter (software-like) in terms
of synthesis?

In any case, you use some ff after synthesis (except if you have a

dedicated counter component in your circuit).
If you don't use explicitly a component instantiation, usage of
divide-by-n counter lets the synthesizer decide with is the better
implementation .

If you use some cascading D-type flip flops structure (remember than a
ff can be a divide-by-2), your 'help' the decision of the synthesizer.

At end, you need certainly keep in mind the timing constraints, the
logic usage, the layout question, the technology target...

If I summarized, to derive 1 Hz from 32.768 kHz clock, you need at least:
* with cascade 15 ff, no combinatory, but capability to clock ff with
different clock signals, the 'new' 1 Hz clock is not synchronize with
32.768 kHz clock
* with counter 15 ff, some possible combinatory to wrap counter +
combinatory to generate the 'new' 1 Hz clock, only one clock requested,
the 'new' 1 Hz clock is synchronize with 32.768 kHz clock

Thank you in advance for any input.


Have you look with google ?

I have found http://www.asicdesign.ru/forum/docs/vhdl/doc05/lec8a.html
that can be interresting.

JaI

 

[Triste]

Just an Illusion <illusion_to_net@yahoo.fr> wrote in message news:<40EE6930.6040408@yahoo.fr>...

Hi Triste,

Triste wrote:

Just an Illusion <illusion_to_net@yahoo.fr> wrote in message news:<40ED4764.2090900@yahoo.fr>...


Hi Triste,

You have certainly some other features, but one of the first is
certainly a problem of clock race.
In case of cascaded divide-by-2, your output clock signal take each time
some little transmission delay; above a certain limit the output clock
is no more synchronized with input one.
With the single long divider (based on counter I think) you can reduce
this clock slide. And it is certainly more simple to resynchronize the
out clock.

JaI




Hi JaI, thanks for the comments.

Actually my question is, to derive 1 Hz from 32.768 KHz, is there any
difference between using cascading D-type flip flops built with
primitive gates and using divide-by-n counter (software-like) in terms
of synthesis?

In any case, you use some ff after synthesis (except if you have a
dedicated counter component in your circuit).
If you don't use explicitly a component instantiation, usage of
divide-by-n counter lets the synthesizer decide with is the better
implementation .

If you use some cascading D-type flip flops structure (remember than a
ff can be a divide-by-2), your 'help' the decision of the synthesizer.

At end, you need certainly keep in mind the timing constraints, the
logic usage, the layout question, the technology target...

If I summarized, to derive 1 Hz from 32.768 kHz clock, you need at least:
* with cascade 15 ff, no combinatory, but capability to clock ff with
different clock signals, the 'new' 1 Hz clock is not synchronize with
32.768 kHz clock
* with counter 15 ff, some possible combinatory to wrap counter +
combinatory to generate the 'new' 1 Hz clock, only one clock requested,
the 'new' 1 Hz clock is synchronize with 32.768 kHz clock



Thank you in advance for any input.


Have you look with google ?
I have found http://www.asicdesign.ru/forum/docs/vhdl/doc05/lec8a.html
that can be interresting.

JaI

Hi JaI,

You've been so helpful. Do appreciate it and thanks for the useful url too!

Triste